exam2.tan.qmsg

来自「使用C8051F020和FPGA设计的低频信号相位测量仪器」· QMSG 代码 · 共 10 行 · 第 1/5 页

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLKIN_12M " "Info: Assuming node \"CLKIN_12M\" is an undefined clock" {  } { { "SIN.vhd" "" { Text "G:/F16_24_P8_ftest/F16_24_P8_ftest/SIN.vhd" 7 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLKIN_12M" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "READ " "Info: Assuming node \"READ\" is an undefined clock" {  } { { "SIN.vhd" "" { Text "G:/F16_24_P8_ftest/F16_24_P8_ftest/SIN.vhd" 22 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "READ" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "SCLK1 " "Info: Assuming node \"SCLK1\" is an undefined clock" {  } { { "SIN.vhd" "" { Text "G:/F16_24_P8_ftest/F16_24_P8_ftest/SIN.vhd" 18 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "SCLK1" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "UPWORD " "Info: Assuming node \"UPWORD\" is an undefined clock" {  } { { "SIN.vhd" "" { Text "G:/F16_24_P8_ftest/F16_24_P8_ftest/SIN.vhd" 11 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "UPWORD" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "W_CLK " "Info: Assuming node \"W_CLK\" is an undefined clock" {  } { { "SIN.vhd" "" { Text "G:/F16_24_P8_ftest/F16_24_P8_ftest/SIN.vhd" 10 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "W_CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "BCLK " "Info: Assuming node \"BCLK\" is an undefined clock" {  } { { "SIN.vhd" "" { Text "G:/F16_24_P8_ftest/F16_24_P8_ftest/SIN.vhd" 16 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "BCLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "SCLK0 " "Info: Assuming node \"SCLK0\" is an undefined clock" {  } { { "SIN.vhd" "" { Text "G:/F16_24_P8_ftest/F16_24_P8_ftest/SIN.vhd" 17 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "SCLK0" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}