exam2.map.eqn

使用C8051F020和FPGA设计的低频信号相位测量仪器

--operation mode is normal

A1L139 = SEL[1] & (SEL[0]) # !SEL[1] & (SEL[0] & H2_q[22] # !SEL[0] & (H2_q[30]));


--H2_q[6] is lpm_counter:TSQ_rtl_1|alt_counter_f10ke:wysi_counter|q[6]
--operation mode is clrb_cntr

H2_q[6]_lut_out = (H2_q[6] $ (ENA & H2L13)) & VCC;
H2_q[6] = DFFEA(H2_q[6]_lut_out, TCLK, !CLR, , ENA, , );

--H2L79Q is lpm_counter:TSQ_rtl_1|alt_counter_f10ke:wysi_counter|q[6]~27
--operation mode is clrb_cntr

H2L79Q = H2_q[6];

--H2L15 is lpm_counter:TSQ_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT
--operation mode is clrb_cntr

H2L15 = CARRY(H2_q[6] & (H2L13));


--A1L79 is Mux~1157
--operation mode is normal

A1L79 = SEL[1] & (A1L78 & (H2_q[6]) # !A1L78 & H2_q[14]) # !SEL[1] & (A1L78);

--A1L140 is Mux~1228
--operation mode is normal

A1L140 = SEL[1] & (A1L78 & (H2_q[6]) # !A1L78 & H2_q[14]) # !SEL[1] & (A1L78);


--A1L80 is Mux~1158
--operation mode is normal

A1L80 = SEL[3] # SEL[2] & (!A1L79) # !SEL[2] & !A1L77;

--A1L141 is Mux~1229
--operation mode is normal

A1L141 = SEL[3] # SEL[2] & (!A1L79) # !SEL[2] & !A1L77;

--A1L142 is Mux~1230
--operation mode is normal

A1L142 = SEL[3] # SEL[2] & (!A1L79) # !SEL[2] & !A1L77;


--H3_q[14] is lpm_counter:SQ_rtl_2|alt_counter_f10ke:wysi_counter|q[14]
--operation mode is clrb_cntr

H3_q[14]_lut_out = (H3_q[14] $ (ENA & H3L29)) & VCC;
H3_q[14] = DFFEA(H3_q[14]_lut_out, SCLK0, !CLR, , ENA, , );

--H3L63Q is lpm_counter:SQ_rtl_2|alt_counter_f10ke:wysi_counter|q[14]~12
--operation mode is clrb_cntr

H3L63Q = H3_q[14];

--H3L31 is lpm_counter:SQ_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[14]~COUT
--operation mode is clrb_cntr

H3L31 = CARRY(H3_q[14] & (H3L29));


--H3_q[6] is lpm_counter:SQ_rtl_2|alt_counter_f10ke:wysi_counter|q[6]
--operation mode is clrb_cntr

H3_q[6]_lut_out = (H3_q[6] $ (ENA & H3L13)) & VCC;
H3_q[6] = DFFEA(H3_q[6]_lut_out, SCLK0, !CLR, , ENA, , );

--H3L47Q is lpm_counter:SQ_rtl_2|alt_counter_f10ke:wysi_counter|q[6]~13
--operation mode is clrb_cntr

H3L47Q = H3_q[6];

--H3L15 is lpm_counter:SQ_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT
--operation mode is clrb_cntr

H3L15 = CARRY(H3_q[6] & (H3L13));


--A1L92 is Mux~1172
--operation mode is normal

A1L92 = (SEL[0] & (!H3_q[6]) # !SEL[0] & !H3_q[14] # !A1L50) & CASCADE(A1L142);

--A1L143 is Mux~1231
--operation mode is normal

A1L143 = (SEL[0] & (!H3_q[6]) # !SEL[0] & !H3_q[14] # !A1L50) & CASCADE(A1L142);


--H1_q[23] is lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|q[23]
--operation mode is clrb_cntr

H1_q[23]_lut_out = (H1_q[23] $ (ENA & H1L47)) & VCC;
H1_q[23] = DFFEA(H1_q[23]_lut_out, BCLK, !CLR, , ENA, , );

--H1L113Q is lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|q[23]~28
--operation mode is clrb_cntr

H1L113Q = H1_q[23];

--H1L49 is lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[23]~COUT
--operation mode is clrb_cntr

H1L49 = CARRY(H1_q[23] & (H1L47));


--H1_q[15] is lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|q[15]
--operation mode is clrb_cntr

H1_q[15]_lut_out = (H1_q[15] $ (ENA & H1L31)) & VCC;
H1_q[15] = DFFEA(H1_q[15]_lut_out, BCLK, !CLR, , ENA, , );

--H1L97Q is lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|q[15]~29
--operation mode is clrb_cntr

H1L97Q = H1_q[15];

--H1L33 is lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[15]~COUT
--operation mode is clrb_cntr

H1L33 = CARRY(H1_q[15] & (H1L31));


--H1_q[31] is lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|q[31]
--operation mode is clrb_cntr

H1_q[31]_lut_out = (H1_q[31] $ (ENA & H1L63)) & VCC;
H1_q[31] = DFFEA(H1_q[31]_lut_out, BCLK, !CLR, , ENA, , );

--H1L129Q is lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|q[31]~30
--operation mode is clrb_cntr

H1L129Q = H1_q[31];


--A1L81 is Mux~1160
--operation mode is normal

A1L81 = SEL[0] & (SEL[1]) # !SEL[0] & (SEL[1] & H1_q[15] # !SEL[1] & (H1_q[31]));

--A1L144 is Mux~1232
--operation mode is normal

A1L144 = SEL[0] & (SEL[1]) # !SEL[0] & (SEL[1] & H1_q[15] # !SEL[1] & (H1_q[31]));


--H1_q[7] is lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|q[7]
--operation mode is clrb_cntr

H1_q[7]_lut_out = (H1_q[7] $ (ENA & H1L15)) & VCC;
H1_q[7] = DFFEA(H1_q[7]_lut_out, BCLK, !CLR, , ENA, , );

--H1L81Q is lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|q[7]~31
--operation mode is clrb_cntr

H1L81Q = H1_q[7];

--H1L17 is lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[7]~COUT
--operation mode is clrb_cntr

H1L17 = CARRY(H1_q[7] & (H1L15));


--A1L82 is Mux~1161
--operation mode is normal

A1L82 = SEL[0] & (A1L81 & (H1_q[7]) # !A1L81 & H1_q[23]) # !SEL[0] & (A1L81);

--A1L145 is Mux~1233
--operation mode is normal

A1L145 = SEL[0] & (A1L81 & (H1_q[7]) # !A1L81 & H1_q[23]) # !SEL[0] & (A1L81);


--H2_q[15] is lpm_counter:TSQ_rtl_1|alt_counter_f10ke:wysi_counter|q[15]
--operation mode is clrb_cntr

H2_q[15]_lut_out = (H2_q[15] $ (ENA & H2L31)) & VCC;
H2_q[15] = DFFEA(H2_q[15]_lut_out, TCLK, !CLR, , ENA, , );

--H2L97Q is lpm_counter:TSQ_rtl_1|alt_counter_f10ke:wysi_counter|q[15]~28
--operation mode is clrb_cntr

H2L97Q = H2_q[15];

--H2L33 is lpm_counter:TSQ_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[15]~COUT
--operation mode is clrb_cntr

H2L33 = CARRY(H2_q[15] & (H2L31));


--H2_q[23] is lpm_counter:TSQ_rtl_1|alt_counter_f10ke:wysi_counter|q[23]
--operation mode is clrb_cntr

H2_q[23]_lut_out = (H2_q[23] $ (ENA & H2L47)) & VCC;
H2_q[23] = DFFEA(H2_q[23]_lut_out, TCLK, !CLR, , ENA, , );

--H2L113Q is lpm_counter:TSQ_rtl_1|alt_counter_f10ke:wysi_counter|q[23]~29
--operation mode is clrb_cntr

H2L113Q = H2_q[23];

--H2L49 is lpm_counter:TSQ_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[23]~COUT
--operation mode is clrb_cntr

H2L49 = CARRY(H2_q[23] & (H2L47));


--H2_q[31] is lpm_counter:TSQ_rtl_1|alt_counter_f10ke:wysi_counter|q[31]
--operation mode is clrb_cntr

H2_q[31]_lut_out = (H2_q[31] $ (ENA & H2L63)) & VCC;
H2_q[31] = DFFEA(H2_q[31]_lut_out, TCLK, !CLR, , ENA, , );

--H2L129Q is lpm_counter:TSQ_rtl_1|alt_counter_f10ke:wysi_counter|q[31]~30
--operation mode is clrb_cntr

H2L129Q = H2_q[31];


--A1L83 is Mux~1162
--operation mode is normal

A1L83 = SEL[1] & (SEL[0]) # !SEL[1] & (SEL[0] & H2_q[23] # !SEL[0] & (H2_q[31]));

--A1L146 is Mux~1234
--operation mode is normal

A1L146 = SEL[1] & (SEL[0]) # !SEL[1] & (SEL[0] & H2_q[23] # !SEL[0] & (H2_q[31]));


--H2_q[7] is lpm_counter:TSQ_rtl_1|alt_counter_f10ke:wysi_counter|q[7]
--operation mode is clrb_cntr

H2_q[7]_lut_out = (H2_q[7] $ (ENA & H2L15)) & VCC;
H2_q[7] = DFFEA(H2_q[7]_lut_out, TCLK, !CLR, , ENA, , );

--H2L81Q is lpm_counter:TSQ_rtl_1|alt_counter_f10ke:wysi_counter|q[7]~31
--operation mode is clrb_cntr

H2L81Q = H2_q[7];

--H2L17 is lpm_counter:TSQ_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[7]~COUT
--operation mode is clrb_cntr

H2L17 = CARRY(H2_q[7] & (H2L15));


--A1L84 is Mux~1163
--operation mode is normal

A1L84 = SEL[1] & (A1L83 & (H2_q[7]) # !A1L83 & H2_q[15]) # !SEL[1] & (A1L83);

--A1L147 is Mux~1235
--operation mode is normal

A1L147 = SEL[1] & (A1L83 & (H2_q[7]) # !A1L83 & H2_q[15]) # !SEL[1] & (A1L83);


--A1L85 is Mux~1164
--operation mode is normal

A1L85 = SEL[3] # SEL[2] & (!A1L84) # !SEL[2] & !A1L82;

--A1L148 is Mux~1236
--operation mode is normal

A1L148 = SEL[3] # SEL[2] & (!A1L84) # !SEL[2] & !A1L82;

--A1L149 is Mux~1237
--operation mode is normal

A1L149 = SEL[3] # SEL[2] & (!A1L84) # !SEL[2] & !A1L82;


--H3_q[15] is lpm_counter:SQ_rtl_2|alt_counter_f10ke:wysi_counter|q[15]
--operation mode is clrb_cntr

H3_q[15]_lut_out = (H3_q[15] $ (ENA & H3L31)) & VCC;
H3_q[15] = DFFEA(H3_q[15]_lut_out, SCLK0, !CLR, , ENA, , );

--H3L65Q is lpm_counter:SQ_rtl_2|alt_counter_f10ke:wysi_counter|q[15]~14
--operation mode is clrb_cntr

H3L65Q = H3_q[15];


--H3_q[7] is lpm_counter:SQ_rtl_2|alt_counter_f10ke:wysi_counter|q[7]
--operation mode is clrb_cntr

H3_q[7]_lut_out = (H3_q[7] $ (ENA & H3L15)) & VCC;
H3_q[7] = DFFEA(H3_q[7]_lut_out, SCLK0, !CLR, , ENA, , );

--H3L49Q is lpm_counter:SQ_rtl_2|alt_counter_f10ke:wysi_counter|q[7]~15
--operation mode is clrb_cntr

H3L49Q = H3_q[7];

--H3L17 is lpm_counter:SQ_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[7]~COUT
--operation mode is clrb_cntr

H3L17 = CARRY(H3_q[7] & (H3L15));


--A1L93 is Mux~1173
--operation mode is normal

A1L93 = (SEL[0] & (!H3_q[7]) # !SEL[0] & !H3_q[15] # !A1L50) & CASCADE(A1L149);

--A1L150 is Mux~1238
--operation mode is normal

A1L150 = (SEL[0] & (!H3_q[7]) # !SEL[0] & !H3_q[15] # !A1L50) & CASCADE(A1L149);


--ENA is ENA
--operation mode is normal

ENA_lut_out = CL;
ENA = DFFEA(ENA_lut_out, SCLK0, , , , , );

--A1L33Q is ENA~1
--operation mode is normal

A1L33Q = ENA;


--TCLK is TCLK
--operation mode is normal

TCLK = BCLK & (SCLK0 $ SCLK1);

--A1L176 is TCLK~8
--operation mode is normal

A1L176 = BCLK & (SCLK0 $ SCLK1);


--DATA[0]$latch is DATA[0]$latch
--operation mode is normal

DATA[0]$latch = A1L173 & !A1L86 # !A1L173 & (DATA[0]$latch);

--A1L10 is DATA[0]$latch~1
--operation mode is normal

A1L10 = A1L173 & !A1L86 # !A1L173 & (DATA[0]$latch);


--DATA[1]$latch is DATA[1]$latch
--operation mode is normal

DATA[1]$latch = A1L173 & !A1L87 # !A1L173 & (DATA[1]$latch);

--A1L13 is DATA[1]$latch~1
--operation mode is normal

A1L13 = A1L173 & !A1L87 # !A1L173 & (DATA[1]$latch);


--DATA[2]$latch is DATA[2]$latch
--operation mode is normal

DATA[2]$latch = A1L173 & !A1L88 # !A1L173 & (DATA[2]$latch);

--A1L16 is DATA[2]$latch~1
--operation mode is normal

A1L16 = A1L173 & !A1L88 # !A1L173 & (DATA[2]$latch);


--DATA[3]$latch is DATA[3]$latch
--operation mode is normal

DATA[3]$latch = A1L173 & !A1L89 # !A1L173 & (DATA[3]$latch);

--A1L19 is DATA[3]$latch~1
--operation mode is normal

A1L19 = A1L173 & !A1L89 # !A1L173 & (DATA[3]$latch);


--DATA[4]$latch is DATA[4]$latch
--operation mode is normal

DATA[4]$latch = A1L173 & !A1L90 # !A1L173 & (DATA[4]$latch);

--A1L22 is DATA[4]$latch~1
--operation mode is normal

A1L22 = A1L173 & !A1L90 # !A1L173 & (DATA[4]$latch);


--DATA[5]$latch is DATA[5]$latch
--operation mode is normal

DATA[5]$latch = A1L173 & !A1L91 # !A1L173 & (DATA[5]$latch);

--A1L25 is DATA[5]$latch~1
--operation mode is normal

A1L25 = A1L173 & !A1L91 # !A1L173 & (DATA[5]$latch);


--DATA[6]$latch is DATA[6]$latch
--operation mode is normal

DATA[6]$latch = A1L173 & !A1L92 # !A1L173 & (DATA[6]$latch);

--A1L28 is DATA[6]$latch~1
--operation mode is normal

A1L28 = A1L173 & !A1L92 # !A1L173 & (DATA[6]$latch);


--DATA[7]$latch is DATA[7]$latch
--operation mode is normal

DATA[7]$latch = A1L173 & !A1L93 # !A1L173 & (DATA[7]$latch);

--A1L31 is DATA[7]$latch~1
--operation mode is normal

A1L31 = A1L173 & !A1L93 # !A1L173 & (DATA[7]$latch);


--~GND is ~GND
--operation mode is normal

~GND = GND;

--A1L189 is ~GND~0
--operation mode is normal

A1L189 = GND;


--UPWORD is UPWORD
--operation mode is