exam2.map.eqn

使用C8051F020和FPGA设计的低频信号相位测量仪器

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--K1_q[0] is SIN_ROM:u3|lpm_rom:lpm_rom_component|altrom:srom|q[0]
K1_q[0]_clock_0 = CLK_6M;
K1_q[0]_write_address = WR_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K1_q[0]_read_address = RD_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K1_q[0] = MEMORY_SEGMENT(, , K1_q[0]_clock_0, , , , , , K1_q[0]_write_address, K1_q[0]_read_address);


--K1_q[1] is SIN_ROM:u3|lpm_rom:lpm_rom_component|altrom:srom|q[1]
K1_q[1]_clock_0 = CLK_6M;
K1_q[1]_write_address = WR_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K1_q[1]_read_address = RD_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K1_q[1] = MEMORY_SEGMENT(, , K1_q[1]_clock_0, , , , , , K1_q[1]_write_address, K1_q[1]_read_address);


--K1_q[2] is SIN_ROM:u3|lpm_rom:lpm_rom_component|altrom:srom|q[2]
K1_q[2]_clock_0 = CLK_6M;
K1_q[2]_write_address = WR_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K1_q[2]_read_address = RD_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K1_q[2] = MEMORY_SEGMENT(, , K1_q[2]_clock_0, , , , , , K1_q[2]_write_address, K1_q[2]_read_address);


--K1_q[3] is SIN_ROM:u3|lpm_rom:lpm_rom_component|altrom:srom|q[3]
K1_q[3]_clock_0 = CLK_6M;
K1_q[3]_write_address = WR_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K1_q[3]_read_address = RD_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K1_q[3] = MEMORY_SEGMENT(, , K1_q[3]_clock_0, , , , , , K1_q[3]_write_address, K1_q[3]_read_address);


--K1_q[4] is SIN_ROM:u3|lpm_rom:lpm_rom_component|altrom:srom|q[4]
K1_q[4]_clock_0 = CLK_6M;
K1_q[4]_write_address = WR_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K1_q[4]_read_address = RD_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K1_q[4] = MEMORY_SEGMENT(, , K1_q[4]_clock_0, , , , , , K1_q[4]_write_address, K1_q[4]_read_address);


--K1_q[5] is SIN_ROM:u3|lpm_rom:lpm_rom_component|altrom:srom|q[5]
K1_q[5]_clock_0 = CLK_6M;
K1_q[5]_write_address = WR_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K1_q[5]_read_address = RD_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K1_q[5] = MEMORY_SEGMENT(, , K1_q[5]_clock_0, , , , , , K1_q[5]_write_address, K1_q[5]_read_address);


--K1_q[6] is SIN_ROM:u3|lpm_rom:lpm_rom_component|altrom:srom|q[6]
K1_q[6]_clock_0 = CLK_6M;
K1_q[6]_write_address = WR_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K1_q[6]_read_address = RD_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K1_q[6] = MEMORY_SEGMENT(, , K1_q[6]_clock_0, , , , , , K1_q[6]_write_address, K1_q[6]_read_address);


--K1_q[7] is SIN_ROM:u3|lpm_rom:lpm_rom_component|altrom:srom|q[7]
K1_q[7]_clock_0 = CLK_6M;
K1_q[7]_write_address = WR_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K1_q[7]_read_address = RD_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K1_q[7] = MEMORY_SEGMENT(, , K1_q[7]_clock_0, , , , , , K1_q[7]_write_address, K1_q[7]_read_address);


--K1_q[8] is SIN_ROM:u3|lpm_rom:lpm_rom_component|altrom:srom|q[8]
K1_q[8]_clock_0 = CLK_6M;
K1_q[8]_write_address = WR_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K1_q[8]_read_address = RD_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K1_q[8] = MEMORY_SEGMENT(, , K1_q[8]_clock_0, , , , , , K1_q[8]_write_address, K1_q[8]_read_address);


--K1_q[9] is SIN_ROM:u3|lpm_rom:lpm_rom_component|altrom:srom|q[9]
K1_q[9]_clock_0 = CLK_6M;
K1_q[9]_write_address = WR_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K1_q[9]_read_address = RD_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K1_q[9] = MEMORY_SEGMENT(, , K1_q[9]_clock_0, , , , , , K1_q[9]_write_address, K1_q[9]_read_address);


--K2_q[0] is SIN_ROM:u6|lpm_rom:lpm_rom_component|altrom:srom|q[0]
K2_q[0]_clock_0 = CLK_6M;
K2_q[0]_write_address = WR_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K2_q[0]_read_address = RD_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K2_q[0] = MEMORY_SEGMENT(, , K2_q[0]_clock_0, , , , , , K2_q[0]_write_address, K2_q[0]_read_address);


--K2_q[1] is SIN_ROM:u6|lpm_rom:lpm_rom_component|altrom:srom|q[1]
K2_q[1]_clock_0 = CLK_6M;
K2_q[1]_write_address = WR_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K2_q[1]_read_address = RD_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K2_q[1] = MEMORY_SEGMENT(, , K2_q[1]_clock_0, , , , , , K2_q[1]_write_address, K2_q[1]_read_address);


--K2_q[2] is SIN_ROM:u6|lpm_rom:lpm_rom_component|altrom:srom|q[2]
K2_q[2]_clock_0 = CLK_6M;
K2_q[2]_write_address = WR_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K2_q[2]_read_address = RD_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K2_q[2] = MEMORY_SEGMENT(, , K2_q[2]_clock_0, , , , , , K2_q[2]_write_address, K2_q[2]_read_address);


--K2_q[3] is SIN_ROM:u6|lpm_rom:lpm_rom_component|altrom:srom|q[3]
K2_q[3]_clock_0 = CLK_6M;
K2_q[3]_write_address = WR_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K2_q[3]_read_address = RD_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K2_q[3] = MEMORY_SEGMENT(, , K2_q[3]_clock_0, , , , , , K2_q[3]_write_address, K2_q[3]_read_address);


--K2_q[4] is SIN_ROM:u6|lpm_rom:lpm_rom_component|altrom:srom|q[4]
K2_q[4]_clock_0 = CLK_6M;
K2_q[4]_write_address = WR_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K2_q[4]_read_address = RD_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K2_q[4] = MEMORY_SEGMENT(, , K2_q[4]_clock_0, , , , , , K2_q[4]_write_address, K2_q[4]_read_address);


--K2_q[5] is SIN_ROM:u6|lpm_rom:lpm_rom_component|altrom:srom|q[5]
K2_q[5]_clock_0 = CLK_6M;
K2_q[5]_write_address = WR_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K2_q[5]_read_address = RD_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K2_q[5] = MEMORY_SEGMENT(, , K2_q[5]_clock_0, , , , , , K2_q[5]_write_address, K2_q[5]_read_address);


--K2_q[6] is SIN_ROM:u6|lpm_rom:lpm_rom_component|altrom:srom|q[6]
K2_q[6]_clock_0 = CLK_6M;
K2_q[6]_write_address = WR_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K2_q[6]_read_address = RD_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K2_q[6] = MEMORY_SEGMENT(, , K2_q[6]_clock_0, , , , , , K2_q[6]_write_address, K2_q[6]_read_address);


--K2_q[7] is SIN_ROM:u6|lpm_rom:lpm_rom_component|altrom:srom|q[7]
K2_q[7]_clock_0 = CLK_6M;
K2_q[7]_write_address = WR_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K2_q[7]_read_address = RD_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K2_q[7] = MEMORY_SEGMENT(, , K2_q[7]_clock_0, , , , , , K2_q[7]_write_address, K2_q[7]_read_address);


--K2_q[8] is SIN_ROM:u6|lpm_rom:lpm_rom_component|altrom:srom|q[8]
K2_q[8]_clock_0 = CLK_6M;
K2_q[8]_write_address = WR_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K2_q[8]_read_address = RD_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K2_q[8] = MEMORY_SEGMENT(, , K2_q[8]_clock_0, , , , , , K2_q[8]_write_address, K2_q[8]_read_address);


--K2_q[9] is SIN_ROM:u6|lpm_rom:lpm_rom_component|altrom:srom|q[9]
K2_q[9]_clock_0 = CLK_6M;
K2_q[9]_write_address = WR_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K2_q[9]_read_address = RD_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K2_q[9] = MEMORY_SEGMENT(, , K2_q[9]_clock_0, , , , , , K2_q[9]_write_address, K2_q[9]_read_address);


--A1L164Q is QOUT~reg0
--operation mode is normal

A1L164Q_lut_out = SCLK0;
A1L164Q = DFFEA(A1L164Q_lut_out, SCLK1, , , , , );

--A1L163Q is QOUT~1
--operation mode is normal

A1L163Q = A1L164Q;


--CLK_6M is CLK_6M
--operation mode is normal

CLK_6M_lut_out = !CLK_6M;
CLK_6M = DFFEA(CLK_6M_lut_out, CLKIN_12M, , , , , );

--A1L4Q is CLK_6M~1
--operation mode is normal

A1L4Q = CLK_6M;


--A1L173 is SEL_WORD~18
--operation mode is normal

A1L173 = !CL & (!SEL[1] & !SEL[2] # !SEL[3]);

--A1L174 is SEL_WORD~19
--operation mode is normal

A1L174 = !CL & (!SEL[1] & !SEL[2] # !SEL[3]);


--H1_q[16] is lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|q[16]
--operation mode is clrb_cntr

H1_q[16]_lut_out = (H1_q[16] $ (ENA & H1L33)) & VCC;
H1_q[16] = DFFEA(H1_q[16]_lut_out, BCLK, !CLR, , ENA, , );

--H1L99Q is lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|q[16]~0
--operation mode is clrb_cntr

H1L99Q = H1_q[16];

--H1L35 is lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[16]~COUT
--operation mode is clrb_cntr

H1L35 = CARRY(H1_q[16] & (H1L33));


--H1_q[8] is lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|q[8]
--operation mode is clrb_cntr

H1_q[8]_lut_out = (H1_q[8] $ (ENA & H1L17)) & VCC;
H1_q[8] = DFFEA(H1_q[8]_lut_out, BCLK, !CLR, , ENA, , );

--H1L83Q is lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|q[8]~1
--operation mode is clrb_cntr

H1L83Q = H1_q[8];

--H1L19 is lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[8]~COUT
--operation mode is clrb_cntr

H1L19 = CARRY(H1_q[8] & (H1L17));


--H1_q[24] is lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|q[24]
--operation mode is clrb_cntr

H1_q[24]_lut_out = (H1_q[24] $ (ENA & H1L49)) & VCC;
H1_q[24] = DFFEA(H1_q[24]_lut_out, BCLK, !CLR, , ENA, , );

--H1L115Q is lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|q[24]~2
--operation mode is clrb_cntr

H1L115Q = H1_q[24];

--H1L51 is lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[24]~COUT
--operation mode is clrb_cntr

H1L51 = CARRY(H1_q[24] & (H1L49));


--A1L45 is Mux~1117
--operation mode is normal

A1L45 = SEL[0] & (SEL[1]) # !SEL[0] & (SEL[1] & H1_q[8] # !SEL[1] & (H1_q[24]));

--A1L94 is Mux~1182
--operation mode is normal

A1L94 = SEL[0] & (SEL[1]) # !SEL[0] & (SEL[1] & H1_q[8] # !SEL[1] & (H1_q[24]));


--H1_q[0] is lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr

H1_q[0]_lut_out = (ENA $ H1_q[0]) & VCC;
H1_q[0] = DFFEA(H1_q[0]_lut_out, BCLK, !CLR, , ENA, , );

--H1L67Q is lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|q[0]~3
--operation mode is clrb_cntr

H1L67Q = H1_q[0];

--H1L3 is lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

H1L3 = CARRY(H1_q[0]);


--A1L46 is Mux~1118
--operation mode is normal

A1L46 = SEL[0] & (A1L45 & (H1_q[0]) # !A1L45 & H1_q[16]) # !SEL[0] & (A1L45);

--A1L95 is Mux~1183
--operation mode is normal

A1L95 = SEL[0] & (A1L45 & (H1_q[0]) # !A1L45 & H1_q[16]) # !SEL[0] & (A1L45);


--H2_q[8] is lpm_counter:TSQ_rtl_1|alt_counter_f10ke:wysi_counter|q[8]
--operation mode is clrb_cntr

H2_q[8]_lut_out = (H2_q[8] $ (ENA & H2L17)) & VCC;
H2_q[8] = DFFEA(H2_q[8]_lut_out, TCLK, !CLR, , ENA, , );

--H2L83Q is lpm_counter:TSQ_rtl_1|alt_counter_f10ke:wysi_counter|q[8]~0
--operation mode is clrb_cntr

H2L83Q = H2_q[8];

--H2L19 is lpm_counter:TSQ_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[8]~COUT
--operation mode is clrb_cntr

H2L19 = CARRY(H2_q[8] & (H2L17));


--H2_q[16] is lpm_counter:TSQ_rtl_1|alt_counter_f10ke:wysi_counter|q[16]
--operation mode is clrb_cntr

H2_q[16]_lut_out = (H2_q[16] $ (ENA & H2L33)) & VCC;
H2_q[16] = DFFEA(H2_q[16]_lut_out, TCLK, !CLR, , ENA, , );

--H2L99Q is lpm_counter:TSQ_rtl_1|alt_counter_f10ke:wysi_counter|q[16]~1
--operation mode is clrb_cntr

H2L99Q = H2_q[16];

--H2L35 is lpm_counter:TSQ_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[16]~COUT
--operation mode is clrb_cntr

H2L35 = CARRY(H2_q[16] & (H2L33));


--H2_q[24] is lpm_counter:TSQ_rtl_1|alt_counter_f10ke:wysi_counter|q[24]
--operation mode is clrb_cntr

H2_q[24]_lut_out = (H2_q[24] $ (ENA & H2L49)) & VCC;
H2_q[24] = DFFEA(H2_q[24]_lut_out, TCLK, !CLR, , ENA, , );

--H2L115Q is lpm_counter:TSQ_rtl_1|alt_counter_f10ke:wysi_counter|q[24]~2
--operation mode is clrb_cntr

H2L115Q = H2_q[24];

--H2L51 is lpm_counter:TSQ_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[24]~COUT
--operation mode is clrb_cntr

H2L51 = CARRY(H2_q[24] & (H2L49));


--A1L47 is Mux~1119
--operation mode is normal

A1L47 = SEL[1] & (SEL[0]) # !SEL[1] & (SEL[0] & H2_q[16] # !SEL[0] & (H2_q[24]));

--A1L96 is Mux~1184
--operation mode is normal

A1L96 = SEL[1] & (SEL[0]) # !SEL[1] & (SEL[0] & H2_q[16] # !SEL[0] & (H2_q[24]));


--H2_q[0] is lpm_counter:TSQ_rtl_1|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr

H2_q[0]_lut_out = (ENA $ H2_q[0]) & VCC;
H2_q[0] = DFFEA(H2_q[0]_lut_out, TCLK, !CLR, , ENA, , );

--H2L67Q is lpm_counter:TSQ_rtl_1|alt_counter_f10ke:wysi_counter|q[0]~3
--operation mode is clrb_cntr

H2L67Q = H2_q[0];

--H2L3 is lpm_counter:TSQ_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

H2L3 = CARRY(H2_q[0]);


--A1L48 is Mux~1120
--operation mode is normal

A1L48 = SEL[1] & (A1L47 & (H2_q[0]) # !A1L47 & H2_q[8]) # !SEL[1] & (A1L47);

--A1L97 is Mux~1185
--operation mode is normal

A1L97 = SEL[1] & (A1L47 & (H2_q[0]) # !A1L47 & H2_q[8]) # !SEL[1] & (A1L47);


--A1L49 is Mux~1121
--operation mode is normal

A1L49 = SEL[3] # SEL[2] & (!A1L48) # !SEL[2] & !A1L46;

--A1L98 is Mux~1186
--operation mode is normal

A1L98 = SEL[3] # SEL[2] & (!A1L48) # !SEL[2] & !A1L46;

--A1L99 is Mux~1187
--operation mode is normal

A1L99 = SEL[3] # SEL[2] & (!A1L48) # !SEL[2] & !A1L46;


--H3_q[8] is lpm_counter:SQ_rtl_2|alt_counter_f10ke:wysi_counter|q[8]
--operation mode is clrb_cntr

H3_q[8]_lut_out = (H3_q[8] $ (ENA & H3L17)) & VCC;
H3_q[8] = DFFEA(H3_q[8]_lut_out, SCLK0, !CLR, , ENA, , );

--H3L51Q is lpm_counter:SQ_rtl_2|alt_counter_f10ke:wysi_counter|q[8]~0
--operation mode is clrb_cntr

H3L51Q = H3_q[8];

--H3L19 is lpm_counter:SQ_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[8]~COUT
--operation mode is clrb_cntr

H3L19 = CARRY(H3_q[8] & (H3L17));


--H3_q[0] is lpm_counter:SQ_rtl_2|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr

H3_q[0]_lut_out = (ENA $ H3_q[0]) & VCC;
H3_q[0] = DFFEA(H3_q[0]_lut_out, SCLK0, !CLR, , ENA, , );

--H3L35Q is lpm_counter:SQ_rtl_2|alt_counter_f10ke:wysi_counter|q[0]~1
--operation mode is clrb_cntr

H3L35Q = H3_q[0];

--H3L3 is lpm_counter:SQ_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

H3L3 = CARRY(H3_q[0]);


--A1L50 is Mux~1122
--operation mode is normal

A1L50 = SEL[3] & (!SEL[1] & !SEL[2]);

--A1L100 is Mux~1188
--operation mode is normal

A1L100 = SEL[3] & (!SEL[1] & !SEL[2]);


--A1L86 is Mux~1166
--operation mode is normal

A1L86 = (SEL[0] & (!H3_q[0]) # !SEL[0] & !H3_q[8] # !A1L50) & CASCADE(A1L99);

--A1L101 is Mux~1189
--operation mode is normal

A1L101 = (SEL[0] & (!H3_q[0]) # !SEL[0] & !H3_q[8] # !A1L50) & CASCADE(A1L99);


--H1_q[17] is lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|q[17]
--operation mode is clrb_cntr

H1_q[17]_lut_out = (H1_q[17] $ (ENA & H1L35)) & VCC;
H1_q[17] = DFFEA(H1_q[17]_lut_out, BCLK, !CLR, , ENA, , );

--H1L101Q is lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|q[17]~4
--operation mode is clrb_cntr