exam2.fit.summary

来自「使用C8051F020和FPGA设计的低频信号相位测量仪器」· SUMMARY 代码 · 共 12 行

Fitter Status : Successful - Thu Jun 07 08:51:24 2007
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : exam2
Top-level Entity Name : SIN
Family : ACEX1K
Device : EP1K30TC144-3
Timing Models : Final
Total logic elements : 289 / 1,728 ( 17 % )
Total pins : 51 / 102 ( 50 % )
Total memory bits : 20,480 / 24,576 ( 83 % )
Total PLLs : 0