adder24b.vhd

来自「使用C8051F020和FPGA设计的低频信号相位测量仪器」· VHDL 代码 · 共 15 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ADDER24B IS
    PORT (  A : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
            B : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
            S : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)     );
END;
ARCHITECTURE behav OF ADDER24B IS
    BEGIN
	S <= A + B;
END behav;