exam2.map.summary

使用C8051F020和FPGA设计的低频信号相位测量仪器

Analysis & Synthesis Status : Successful - Thu Jun 07 08:51:07 2007
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : exam2
Top-level Entity Name : SIN
Family : ACEX1K
Total logic elements : 269
Total pins : 51
Total memory bits : 20,480
Total PLLs : 0