reg24b.vhd

来自「使用C8051F020和FPGA设计的低频信号相位测量仪器」· VHDL 代码 · 共 17 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG24B IS
    PORT (  Load : IN STD_LOGIC;
             DIN : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
            DOUT : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) );
END;
ARCHITECTURE behav OF REG24B IS
BEGIN
    PROCESS(Load, DIN)
   BEGIN
   IF Load'EVENT AND Load = '1' THEN DOUT <= DIN; END IF;
    END PROCESS;
END behav;