exam2.map.qmsg

使用C8051F020和FPGA设计的低频信号相位测量仪器

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "W_CLK SIN.vhd(139) " "Warning (10492): VHDL Process Statement warning at SIN.vhd(139): signal \"W_CLK\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 139 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_L2_VRFC_DRIVERLESS_OUTPUT_PORT" "LIGHT SIN.vhd(14) " "Warning (10034): Output port \"LIGHT\" at SIN.vhd(14) has no driver" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 14 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "DATA\[0\] SIN.vhd(78) " "Info (10041): Verilog HDL or VHDL info at SIN.vhd(78): inferred latch for \"DATA\[0\]\"" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 78 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "DATA\[1\] SIN.vhd(78) " "Info (10041): Verilog HDL or VHDL info at SIN.vhd(78): inferred latch for \"DATA\[1\]\"" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 78 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "DATA\[2\] SIN.vhd(78) " "Info (10041): Verilog HDL or VHDL info at SIN.vhd(78): inferred latch for \"DATA\[2\]\"" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 78 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "DATA\[3\] SIN.vhd(78) " "Info (10041): Verilog HDL or VHDL info at SIN.vhd(78): inferred latch for \"DATA\[3\]\"" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 78 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "DATA\[4\] SIN.vhd(78) " "Info (10041): Verilog HDL or VHDL info at SIN.vhd(78): inferred latch for \"DATA\[4\]\"" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 78 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "DATA\[5\] SIN.vhd(78) " "Info (10041): Verilog HDL or VHDL info at SIN.vhd(78): inferred latch for \"DATA\[5\]\"" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 78 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "DATA\[6\] SIN.vhd(78) " "Info (10041): Verilog HDL or VHDL info at SIN.vhd(78): inferred latch for \"DATA\[6\]\"" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 78 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "DATA\[7\] SIN.vhd(78) " "Info (10041): Verilog HDL or VHDL info at SIN.vhd(78): inferred latch for \"DATA\[7\]\"" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 78 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ADDER24B ADDER24B:u1 " "Info: Elaborating entity \"ADDER24B\" for hierarchy \"ADDER24B:u1\"" {  } { { "SIN.vhd" "u1" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 160 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "REG24B REG24B:u2 " "Info: Elaborating entity \"REG24B\" for hierarchy \"REG24B:u2\"" {  } { { "SIN.vhd" "u2" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 161 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "SIN_ROM.vhd 2 1 " "Warning: Using design file SIN_ROM.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sin_rom-SYN " "Info: Found design unit 1: sin_rom-SYN" {  } { { "SIN_ROM.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN_ROM.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 SIN_ROM " "Info: Found entity 1: SIN_ROM" {  } { { "SIN_ROM.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN_ROM.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SIN_ROM SIN_ROM:u3 " "Info: Elaborating entity \"SIN_ROM\" for hierarchy \"SIN_ROM:u3\"" {  } { { "SIN.vhd" "u3" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 162 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/70/quartus/libraries/megafunctions/lpm_rom.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/70/quartus/libraries/megafunctions/lpm_rom.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom " "Info: Found entity 1: lpm_rom" {  } { { "lpm_rom.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/lpm_rom.tdf" 43 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom SIN_ROM:u3\|lpm_rom:lpm_rom_component " "Info: Elaborating entity \"lpm_rom\" for hierarchy \"SIN_ROM:u3\|lpm_rom:lpm_rom_component\"" {  } { { "SIN_ROM.vhd" "lpm_rom_component" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN_ROM.vhd" 75 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "SIN_ROM:u3\|lpm_rom:lpm_rom_component " "Info: Elaborated megafunction instantiation \"SIN_ROM:u3\|lpm_rom:lpm_rom_component\"" {  } { { "SIN_ROM.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN_ROM.vhd" 75 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/70/quartus/libraries/megafunctions/altrom.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/70/quartus/libraries/megafunctions/altrom.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altrom " "Info: Found entity 1: altrom" {  } { { "altrom.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/altrom.tdf" 77 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altrom SIN_ROM:u3\|lpm_rom:lpm_rom_component\|altrom:srom " "Info: Elaborating entity \"altrom\" for hierarchy \"SIN_ROM:u3\|lpm_rom:lpm_rom_component\|altrom:srom\"" {  } { { "lpm_rom.tdf" "srom" { Text "d:/altera/70/quartus/libraries/megafunctions/lpm_rom.tdf" 54 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "SIN_ROM:u3\|lpm_rom:lpm_rom_component\|altrom:srom SIN_ROM:u3\|lpm_rom:lpm_rom_component " "Info: Elaborated megafunction instantiation \"SIN_ROM:u3\|lpm_rom:lpm_rom_component\|altrom:srom\", which is child of megafunction instantiation \"SIN_ROM:u3\|lpm_rom:lpm_rom_component\"" {  } { { "lpm_rom.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/lpm_rom.tdf" 54 3 0 } } { "SIN_ROM.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN_ROM.vhd" 75 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "SIN_ROM:u3\|lpm_rom:lpm_rom_component " "Info: Instantiated megafunction \"SIN_ROM:u3\|lpm_rom:lpm_rom_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family ACEX1K " "Info: Parameter \"intended_device_family\" = \"ACEX1K\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_address_control REGISTERED " "Info: Parameter \"lpm_address_control\" = \"REGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_file sin_romdata.mif " "Info: Parameter \"lpm_file\" = \"sin_romdata.mif\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_outdata UNREGISTERED " "Info: Parameter \"lpm_outdata\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_ROM " "Info: Parameter \"lpm_type\" = \"LPM_ROM\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 10 " "Info: Parameter \"lpm_width\" = \"10\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthad 10 " "Info: Parameter \"lpm_widthad\" = \"10\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "SIN_ROM.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN_ROM.vhd" 75 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ADDER10B ADDER10B:u4 " "Info: Elaborating entity \"ADDER10B\" for hierarchy \"ADDER10B:u4\"" {  } { { "SIN.vhd" "u4" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 163 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "REG10B REG10B:u5 " "Info: Elaborating entity \"REG10B\" for hierarchy \"REG10B:u5\"" {  } { { "SIN.vhd" "u5" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 164 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}