exam2.map.qmsg

使用C8051F020和FPGA设计的低频信号相位测量仪器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jun 08 09:58:48 2007 " "Info: Processing started: Fri Jun 08 09:58:48 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off exam2 -c exam2 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off exam2 -c exam2" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SIN.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file SIN.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 SIN-one " "Info: Found design unit 1: SIN-one" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 26 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 SIN " "Info: Found entity 1: SIN" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/ADDER32B.vhd " "Warning: Can't analyze file -- file G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/ADDER32B.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ADDER10B.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ADDER10B.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ADDER10B-behav " "Info: Found design unit 1: ADDER10B-behav" {  } { { "ADDER10B.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/ADDER10B.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ADDER10B " "Info: Found entity 1: ADDER10B" {  } { { "ADDER10B.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/ADDER10B.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/REG32B.vhd " "Warning: Can't analyze file -- file G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/REG32B.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "REG10B.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file REG10B.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 REG10B-behav " "Info: Found design unit 1: REG10B-behav" {  } { { "REG10B.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/REG10B.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 REG10B " "Info: Found entity 1: REG10B" {  } { { "REG10B.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/REG10B.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "REG24B.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file REG24B.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 REG24B-behav " "Info: Found design unit 1: REG24B-behav" {  } { { "REG24B.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/REG24B.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 REG24B " "Info: Found entity 1: REG24B" {  } { { "REG24B.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/REG24B.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ADDER24B.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ADDER24B.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ADDER24B-behav " "Info: Found design unit 1: ADDER24B-behav" {  } { { "ADDER24B.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/ADDER24B.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ADDER24B " "Info: Found entity 1: ADDER24B" {  } { { "ADDER24B.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/ADDER24B.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "SIN " "Info: Elaborating entity \"SIN\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "BZQ SIN.vhd(82) " "Warning (10492): VHDL Process Statement warning at SIN.vhd(82): signal \"BZQ\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 82 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "BZQ SIN.vhd(83) " "Warning (10492): VHDL Process Statement warning at SIN.vhd(83): signal \"BZQ\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 83 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "BZQ SIN.vhd(84) " "Warning (10492): VHDL Process Statement warning at SIN.vhd(84): signal \"BZQ\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 84 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "BZQ SIN.vhd(85) " "Warning (10492): VHDL Process Statement warning at SIN.vhd(85): signal \"BZQ\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 85 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "TSQ SIN.vhd(86) " "Warning (10492): VHDL Process Statement warning at SIN.vhd(86): signal \"TSQ\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 86 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "TSQ SIN.vhd(87) " "Warning (10492): VHDL Process Statement warning at SIN.vhd(87): signal \"TSQ\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 87 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "TSQ SIN.vhd(88) " "Warning (10492): VHDL Process Statement warning at SIN.vhd(88): signal \"TSQ\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 88 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "TSQ SIN.vhd(89) " "Warning (10492): VHDL Process Statement warning at SIN.vhd(89): signal \"TSQ\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 89 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "SQ SIN.vhd(90) " "Warning (10492): VHDL Process Statement warning at SIN.vhd(90): signal \"SQ\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 90 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "SQ SIN.vhd(91) " "Warning (10492): VHDL Process Statement warning at SIN.vhd(91): signal \"SQ\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 91 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "DATA SIN.vhd(78) " "Warning (10631): VHDL Process Statement warning at SIN.vhd(78): inferring latch(es) for signal or variable \"DATA\", which holds its previous value in one or more paths through the process" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 78 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "RESET SIN.vhd(137) " "Warning (10492): VHDL Process Statement warning at SIN.vhd(137): signal \"RESET\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 137 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}