exam2.tan.qmsg

使用C8051F020和FPGA设计的低频信号相位测量仪器

{ "Info" "ITAN_NO_REG2REG_EXIST" "UPDATA " "Info: No valid register-to-register data paths exist for clock \"UPDATA\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "W_CLK register STATE.s3 register PWORD\[0\] 196.08 MHz 5.1 ns Internal " "Info: Clock \"W_CLK\" has Internal fmax of 196.08 MHz between source register \"STATE.s3\" and destination register \"PWORD\[0\]\" (period= 5.1 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.900 ns + Longest register register " "Info: + Longest register to register delay is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns STATE.s3 1 REG LC3_B34 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_B34; Fanout = 3; REG Node = 'STATE.s3'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { STATE.s3 } "NODE_NAME" } } { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 1.900 ns PWORD\[7\]~49 2 COMB LC1_B34 8 " "Info: 2: + IC(0.300 ns) + CELL(1.600 ns) = 1.900 ns; Loc. = LC1_B34; Fanout = 8; COMB Node = 'PWORD\[7\]~49'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { STATE.s3 PWORD[7]~49 } "NODE_NAME" } } { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 139 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.000 ns) 3.900 ns PWORD\[0\] 3 REG LC6_B35 1 " "Info: 3: + IC(1.000 ns) + CELL(1.000 ns) = 3.900 ns; Loc. = LC6_B35; Fanout = 1; REG Node = 'PWORD\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { PWORD[7]~49 PWORD[0] } "NODE_NAME" } } { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 139 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns ( 66.67 % ) " "Info: Total cell delay = 2.600 ns ( 66.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 33.33 % ) " "Info: Total interconnect delay = 1.300 ns ( 33.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { STATE.s3 PWORD[7]~49 PWORD[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.900 ns" { STATE.s3 PWORD[7]~49 PWORD[0] } { 0.000ns 0.300ns 1.000ns } { 0.000ns 1.600ns 1.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.100 ns - Smallest " "Info: - Smallest clock skew is -0.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "W_CLK destination 7.200 ns + Shortest register " "Info: + Shortest clock path from clock \"W_CLK\" to destination register is 7.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns W_CLK 1 CLK PIN_36 30 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_36; Fanout = 30; CLK Node = 'W_CLK'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { W_CLK } "NODE_NAME" } } { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(0.000 ns) 7.200 ns PWORD\[0\] 2 REG LC6_B35 1 " "Info: 2: + IC(2.300 ns) + CELL(0.000 ns) = 7.200 ns; Loc. = LC6_B35; Fanout = 1; REG Node = 'PWORD\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.300 ns" { W_CLK PWORD[0] } "NODE_NAME" } } { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 139 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.900 ns ( 68.06 % ) " "Info: Total cell delay = 4.900 ns ( 68.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.300 ns ( 31.94 % ) " "Info: Total interconnect delay = 2.300 ns ( 31.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.200 ns" { W_CLK PWORD[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.200 ns" { W_CLK W_CLK~out PWORD[0] } { 0.000ns 0.000ns 2.300ns } { 0.000ns 4.900ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "W_CLK source 7.300 ns - Longest register " "Info: - Longest clock path from clock \"W_CLK\" to source register is 7.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns W_CLK 1 CLK PIN_36 30 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_36; Fanout = 30; CLK Node = 'W_CLK'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { W_CLK } "NODE_NAME" } } { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(0.000 ns) 7.300 ns STATE.s3 2 REG LC3_B34 3 " "Info: 2: + IC(2.400 ns) + CELL(0.000 ns) = 7.300 ns; Loc. = LC3_B34; Fanout = 3; REG Node = 'STATE.s3'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { W_CLK STATE.s3 } "NODE_NAME" } } { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.900 ns ( 67.12 % ) " "Info: Total cell delay = 4.900 ns ( 67.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.400 ns ( 32.88 % ) " "Info: Total interconnect delay = 2.400 ns ( 32.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.300 ns" { W_CLK STATE.s3 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.300 ns" { W_CLK W_CLK~out STATE.s3 } { 0.000ns 0.000ns 2.400ns } { 0.000ns 4.900ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.200 ns" { W_CLK PWORD[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.200 ns" { W_CLK W_CLK~out PWORD[0] } { 0.000ns 0.000ns 2.300ns } { 0.000ns 4.900ns 0.000ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.300 ns" { W_CLK STATE.s3 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.300 ns" { W_CLK W_CLK~out STATE.s3 } { 0.000ns 0.000ns 2.400ns } { 0.000ns 4.900ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 28 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 139 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { STATE.s3 PWORD[7]~49 PWORD[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.900 ns" { STATE.s3 PWORD[7]~49 PWORD[0] } { 0.000ns 0.300ns 1.000ns } { 0.000ns 1.600ns 1.000ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.200 ns" { W_CLK PWORD[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.200 ns" { W_CLK W_CLK~out PWORD[0] } { 0.000ns 0.000ns 2.300ns } { 0.000ns 4.900ns 0.000ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.300 ns" { W_CLK STATE.s3 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.300 ns" { W_CLK W_CLK~out STATE.s3 } { 0.000ns 0.000ns 2.400ns } { 0.000ns 4.900ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "BCLK register lpm_counter:BZQ_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] register lpm_counter:BZQ_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[31\] 104.17 MHz 9.6 ns Internal " "Info: Clock \"BCLK\" has Internal fmax of 104.17 MHz between source register \"lpm_counter:BZQ_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]\" and destination register \"lpm_counter:BZQ_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[31\]\" (period= 9.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.500 ns + Longest register register " "Info: + Longest register to register delay is 8.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:BZQ_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 1 REG LC1_E11 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_E11; Fanout = 3; REG Node = 'lpm_counter:BZQ_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns lpm_counter:BZQ_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[0\]~COUT 2 COMB LC1_E11 2 " "Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = LC1_E11; Fanout = 2; COMB Node = 'lpm_counter:BZQ_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[0\]~COUT'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.200 ns" { lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|q[0] lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 329 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.400 ns lpm_counter:BZQ_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[1\]~COUT 3 COMB LC2_E11 2 " "Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 0.400 ns; Loc. = LC2_E11; Fanout = 2; COMB Node = 'lpm_counter:BZQ_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[1\]~COUT'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.200 ns" { lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 329 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.600 ns lpm_counter:BZQ_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[2\]~COUT 4 COMB LC3_E11 2 " "Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 0.600 ns; Loc. = LC3_E11; Fanout = 2; COMB Node = 'lpm_counter:BZQ_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[2\]~COUT'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.200 ns" { lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 329 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.800 ns lpm_counter:BZQ_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[3\]~COUT 5 COMB LC4_E11 2 " "Info: 5: + IC(0.000 ns) + CELL(0.200 ns) = 0.800 ns; Loc. = LC4_E11; Fanout = 2; COMB Node = 'lpm_counter:BZQ_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[3\]~COUT'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.200 ns" { lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 329 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 1.000 ns lpm_counter:BZQ_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[4\]~COUT 6 COMB LC5_E11 2 " "Info: 6: + IC(0.000 ns) + CELL(0.200 ns) = 1.000 ns; Loc. = LC5_E11; Fanout = 2; COMB Node = 'lpm_counter:BZQ_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[4\]~COUT'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.200 ns" { lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT lpm_counter:BZQ_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" {