exam2.tan.qmsg

来自「使用C8051F020和FPGA设计的低频信号相位测量仪器」· QMSG 代码 · 共 12 行 · 第 1/5 页

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "DATA\[0\]\$latch " "Warning: Node \"DATA\[0\]\$latch\" is a latch" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 78 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DATA\[1\]\$latch " "Warning: Node \"DATA\[1\]\$latch\" is a latch" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 78 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DATA\[2\]\$latch " "Warning: Node \"DATA\[2\]\$latch\" is a latch" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 78 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DATA\[3\]\$latch " "Warning: Node \"DATA\[3\]\$latch\" is a latch" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 78 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DATA\[4\]\$latch " "Warning: Node \"DATA\[4\]\$latch\" is a latch" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 78 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DATA\[5\]\$latch " "Warning: Node \"DATA\[5\]\$latch\" is a latch" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 78 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DATA\[6\]\$latch " "Warning: Node \"DATA\[6\]\$latch\" is a latch" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 78 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DATA\[7\]\$latch " "Warning: Node \"DATA\[7\]\$latch\" is a latch" {  } { { "SIN.vhd" "" { Text "G:/seoul/EP1K30TC144/项目一/低频数字相位测试仪/f16_P10_fretest/定稿1/SIN.vhd" 78 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}