exam2.map.qmsg

使用C8051F020和FPGA设计的低频信号相位测量仪器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jun 07 08:51:02 2007 " "Info: Processing started: Thu Jun 07 08:51:02 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off exam2 -c exam2 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off exam2 -c exam2" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SIN.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file SIN.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 SIN-one " "Info: Found design unit 1: SIN-one" {  } { { "SIN.vhd" "" { Text "G:/F16_24_P8_ftest/F16_24_P8_ftest/SIN.vhd" 28 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 SIN " "Info: Found entity 1: SIN" {  } { { "SIN.vhd" "" { Text "G:/F16_24_P8_ftest/F16_24_P8_ftest/SIN.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "G:/F16_24_P8_ftest/F16_24_P8_ftest/ADDER32B.vhd " "Warning: Can't analyze file -- file G:/F16_24_P8_ftest/F16_24_P8_ftest/ADDER32B.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ADDER10B.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ADDER10B.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ADDER10B-behav " "Info: Found design unit 1: ADDER10B-behav" {  } { { "ADDER10B.vhd" "" { Text "G:/F16_24_P8_ftest/F16_24_P8_ftest/ADDER10B.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ADDER10B " "Info: Found entity 1: ADDER10B" {  } { { "ADDER10B.vhd" "" { Text "G:/F16_24_P8_ftest/F16_24_P8_ftest/ADDER10B.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "G:/F16_24_P8_ftest/F16_24_P8_ftest/REG32B.vhd " "Warning: Can't analyze file -- file G:/F16_24_P8_ftest/F16_24_P8_ftest/REG32B.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "REG10B.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file REG10B.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 REG10B-behav " "Info: Found design unit 1: REG10B-behav" {  } { { "REG10B.vhd" "" { Text "G:/F16_24_P8_ftest/F16_24_P8_ftest/REG10B.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 REG10B " "Info: Found entity 1: REG10B" {  } { { "REG10B.vhd" "" { Text "G:/F16_24_P8_ftest/F16_24_P8_ftest/REG10B.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "REG24B.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file REG24B.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 REG24B-behav " "Info: Found design unit 1: REG24B-behav" {  } { { "REG24B.vhd" "" { Text "G:/F16_24_P8_ftest/F16_24_P8_ftest/REG24B.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 REG24B " "Info: Found entity 1: REG24B" {  } { { "REG24B.vhd" "" { Text "G:/F16_24_P8_ftest/F16_24_P8_ftest/REG24B.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ADDER24B.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ADDER24B.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ADDER24B-behav " "Info: Found design unit 1: ADDER24B-behav" {  } { { "ADDER24B.vhd" "" { Text "G:/F16_24_P8_ftest/F16_24_P8_ftest/ADDER24B.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ADDER24B " "Info: Found entity 1: ADDER24B" {  } { { "ADDER24B.vhd" "" { Text "G:/F16_24_P8_ftest/F16_24_P8_ftest/ADDER24B.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "SIN " "Info: Elaborating entity \"SIN\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "READ SIN.vhd(85) " "Warning (10492): VHDL Process Statement warning at SIN.vhd(85): signal \"READ\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "SIN.vhd" "" { Text "G:/F16_24_P8_ftest/F16_24_P8_ftest/SIN.vhd" 85 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "RESET SIN.vhd(148) " "Warning (10492): VHDL Process Statement warning at SIN.vhd(148): signal \"RESET\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "SIN.vhd" "" { Text "G:/F16_24_P8_ftest/F16_24_P8_ftest/SIN.vhd" 148 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "W_CLK SIN.vhd(150) " "Warning (10492): VHDL Process Statement warning at SIN.vhd(150): signal \"W_CLK\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "SIN.vhd" "" { Text "G:/F16_24_P8_ftest/F16_24_P8_ftest/SIN.vhd" 150 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ADDER24B ADDER24B:u1 " "Info: Elaborating entity \"ADDER24B\" for hierarchy \"ADDER24B:u1\"" {  } { { "SIN.vhd" "u1" { Text "G:/F16_24_P8_ftest/F16_24_P8_ftest/SIN.vhd" 171 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "REG24B REG24B:u2 " "Info: Elaborating entity \"REG24B\" for hierarchy \"REG24B:u2\"" {  } { { "SIN.vhd" "u2" { Text "G:/F16_24_P8_ftest/F16_24_P8_ftest/SIN.vhd" 172 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "SIN_ROM.vhd 2 1 " "Warning: Using design file SIN_ROM.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sin_rom-SYN " "Info: Found design unit 1: sin_rom-SYN" {  } { { "SIN_ROM.vhd" "" { Text "G:/F16_24_P8_ftest/F16_24_P8_ftest/SIN_ROM.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 SIN_ROM " "Info: Found entity 1: SIN_ROM" {  } { { "SIN_ROM.vhd" "" { Text "G:/F16_24_P8_ftest/F16_24_P8_ftest/SIN_ROM.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SIN_ROM SIN_ROM:u3 " "Info: Elaborating entity \"SIN_ROM\" for hierarchy \"SIN_ROM:u3\"" {  } { { "SIN.vhd" "u3" { Text "G:/F16_24_P8_ftest/F16_24_P8_ftest/SIN.vhd" 173 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/70/quartus/libraries/megafunctions/lpm_rom.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/70/quartus/libraries/megafunctions/lpm_rom.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom " "Info: Found entity 1: lpm_rom" {  } { { "lpm_rom.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/lpm_rom.tdf" 43 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom SIN_ROM:u3\|lpm_rom:lpm_rom_component " "Info: Elaborating entity \"lpm_rom\" for hierarchy \"SIN_ROM:u3\|lpm_rom:lpm_rom_component\"" {  } { { "SIN_ROM.vhd" "lpm_rom_component" { Text "G:/F16_24_P8_ftest/F16_24_P8_ftest/SIN_ROM.vhd" 75 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "SIN_ROM:u3\|lpm_rom:lpm_rom_component " "Info: Elaborated megafunction instantiation \"SIN_ROM:u3\|lpm_rom:lpm_rom_component\"" {  } { { "SIN_ROM.vhd" "" { Text "G:/F16_24_P8_ftest/F16_24_P8_ftest/SIN_ROM.vhd" 75 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/70/quartus/libraries/megafunctions/altrom.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/70/quartus/libraries/megafunctions/altrom.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altrom " "Info: Found entity 1: altrom" {  } { { "altrom.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/altrom.tdf" 77 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altrom SIN_ROM:u3\|lpm_rom:lpm_rom_component\|altrom:srom " "Info: Elaborating entity \"altrom\" for hierarchy \"SIN_ROM:u3\|lpm_rom:lpm_rom_component\|altrom:srom\"" {  } { { "lpm_rom.tdf" "srom" { Text "d:/altera/70/quartus/libraries/megafunctions/lpm_rom.tdf" 54 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "SIN_ROM:u3\|lpm_rom:lpm_rom_component\|altrom:srom SIN_ROM:u3\|lpm_rom:lpm_rom_component " "Info: Elaborated megafunction instantiation \"SIN_ROM:u3\|lpm_rom:lpm_rom_component\|altrom:srom\", which is child of megafunction instantiation \"SIN_ROM:u3\|lpm_rom:lpm_rom_component\"" {  } { { "lpm_rom.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/lpm_rom.tdf" 54 3 0 } } { "SIN_ROM.vhd" "" { Text "G:/F16_24_P8_ftest/F16_24_P8_ftest/SIN_ROM.vhd" 75 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}