exam2.hier_info

使用C8051F020和FPGA设计的低频信号相位测量仪器

ENA => BZQ[12].ENA
ENA => BZQ[13].ENA
ENA => BZQ[14].ENA
ENA => BZQ[15].ENA
ENA => BZQ[16].ENA
ENA => BZQ[17].ENA
ENA => BZQ[18].ENA
ENA => BZQ[19].ENA
ENA => BZQ[20].ENA
ENA => BZQ[21].ENA
ENA => BZQ[22].ENA
ENA => BZQ[23].ENA
ENA => BZQ[24].ENA
ENA => BZQ[25].ENA
ENA => BZQ[26].ENA
ENA => BZQ[27].ENA
ENA => BZQ[28].ENA
ENA => BZQ[29].ENA
ENA => BZQ[30].ENA
ENA => BZQ[31].ENA
SEL[0] => Mux0.IN9
SEL[0] => Mux1.IN9
SEL[0] => Mux2.IN9
SEL[0] => Mux3.IN9
SEL[0] => Mux4.IN9
SEL[0] => Mux5.IN9
SEL[0] => Mux6.IN9
SEL[0] => Mux7.IN9
SEL[1] => Mux0.IN8
SEL[1] => Mux1.IN8
SEL[1] => Mux2.IN8
SEL[1] => Mux3.IN8
SEL[1] => Mux4.IN8
SEL[1] => Mux5.IN8
SEL[1] => Mux6.IN8
SEL[1] => Mux7.IN8
SEL[2] => Mux0.IN7
SEL[2] => Mux1.IN7
SEL[2] => Mux2.IN7
SEL[2] => Mux3.IN7
SEL[2] => Mux4.IN7
SEL[2] => Mux5.IN7
SEL[2] => Mux6.IN7
SEL[2] => Mux7.IN7
SEL[3] => Mux0.IN6
SEL[3] => Mux1.IN6
SEL[3] => Mux2.IN6
SEL[3] => Mux3.IN6
SEL[3] => Mux4.IN6
SEL[3] => Mux5.IN6
SEL[3] => Mux6.IN6
SEL[3] => Mux7.IN6
READ => DATA[0]~reg0.CLK
READ => DATA[1]~reg0.CLK
READ => DATA[2]~reg0.CLK
READ => DATA[3]~reg0.CLK
READ => DATA[4]~reg0.CLK
READ => DATA[5]~reg0.CLK
READ => DATA[6]~reg0.CLK
READ => DATA[7]~reg0.CLK
DATA[0] <= DATA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DATA[1] <= DATA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DATA[2] <= DATA[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DATA[3] <= DATA[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DATA[4] <= DATA[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DATA[5] <= DATA[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DATA[6] <= DATA[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DATA[7] <= DATA[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
QOUT <= QOUT~reg0.DB_MAX_OUTPUT_PORT_TYPE


|SIN|ADDER24B:u1
A[0] => Add0.IN24
A[1] => Add0.IN23
A[2] => Add0.IN22
A[3] => Add0.IN21
A[4] => Add0.IN20
A[5] => Add0.IN19
A[6] => Add0.IN18
A[7] => Add0.IN17
A[8] => Add0.IN16
A[9] => Add0.IN15
A[10] => Add0.IN14
A[11] => Add0.IN13
A[12] => Add0.IN12
A[13] => Add0.IN11
A[14] => Add0.IN10
A[15] => Add0.IN9
A[16] => Add0.IN8
A[17] => Add0.IN7
A[18] => Add0.IN6
A[19] => Add0.IN5
A[20] => Add0.IN4
A[21] => Add0.IN3
A[22] => Add0.IN2
A[23] => Add0.IN1
B[0] => Add0.IN48
B[1] => Add0.IN47
B[2] => Add0.IN46
B[3] => Add0.IN45
B[4] => Add0.IN44
B[5] => Add0.IN43
B[6] => Add0.IN42
B[7] => Add0.IN41
B[8] => Add0.IN40
B[9] => Add0.IN39
B[10] => Add0.IN38
B[11] => Add0.IN37
B[12] => Add0.IN36
B[13] => Add0.IN35
B[14] => Add0.IN34
B[15] => Add0.IN33
B[16] => Add0.IN32
B[17] => Add0.IN31
B[18] => Add0.IN30
B[19] => Add0.IN29
B[20] => Add0.IN28
B[21] => Add0.IN27
B[22] => Add0.IN26
B[23] => Add0.IN25
S[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[6] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[7] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[8] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[9] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[10] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[11] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[12] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[13] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[14] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[15] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[16] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[17] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[18] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[19] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[20] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[21] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[22] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[23] <= Add0.DB_MAX_OUTPUT_PORT_TYPE


|SIN|REG24B:u2
Load => DOUT[0]~reg0.CLK
Load => DOUT[1]~reg0.CLK
Load => DOUT[2]~reg0.CLK
Load => DOUT[3]~reg0.CLK
Load => DOUT[4]~reg0.CLK
Load => DOUT[5]~reg0.CLK
Load => DOUT[6]~reg0.CLK
Load => DOUT[7]~reg0.CLK
Load => DOUT[8]~reg0.CLK
Load => DOUT[9]~reg0.CLK
Load => DOUT[10]~reg0.CLK
Load => DOUT[11]~reg0.CLK
Load => DOUT[12]~reg0.CLK
Load => DOUT[13]~reg0.CLK
Load => DOUT[14]~reg0.CLK
Load => DOUT[15]~reg0.CLK
Load => DOUT[16]~reg0.CLK
Load => DOUT[17]~reg0.CLK
Load => DOUT[18]~reg0.CLK
Load => DOUT[19]~reg0.CLK
Load => DOUT[20]~reg0.CLK
Load => DOUT[21]~reg0.CLK
Load => DOUT[22]~reg0.CLK
Load => DOUT[23]~reg0.CLK
DIN[0] => DOUT[0]~reg0.DATAIN
DIN[1] => DOUT[1]~reg0.DATAIN
DIN[2] => DOUT[2]~reg0.DATAIN
DIN[3] => DOUT[3]~reg0.DATAIN
DIN[4] => DOUT[4]~reg0.DATAIN
DIN[5] => DOUT[5]~reg0.DATAIN
DIN[6] => DOUT[6]~reg0.DATAIN
DIN[7] => DOUT[7]~reg0.DATAIN
DIN[8] => DOUT[8]~reg0.DATAIN
DIN[9] => DOUT[9]~reg0.DATAIN
DIN[10] => DOUT[10]~reg0.DATAIN
DIN[11] => DOUT[11]~reg0.DATAIN
DIN[12] => DOUT[12]~reg0.DATAIN
DIN[13] => DOUT[13]~reg0.DATAIN
DIN[14] => DOUT[14]~reg0.DATAIN
DIN[15] => DOUT[15]~reg0.DATAIN
DIN[16] => DOUT[16]~reg0.DATAIN
DIN[17] => DOUT[17]~reg0.DATAIN
DIN[18] => DOUT[18]~reg0.DATAIN
DIN[19] => DOUT[19]~reg0.DATAIN
DIN[20] => DOUT[20]~reg0.DATAIN
DIN[21] => DOUT[21]~reg0.DATAIN
DIN[22] => DOUT[22]~reg0.DATAIN
DIN[23] => DOUT[23]~reg0.DATAIN
DOUT[0] <= DOUT[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[1] <= DOUT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[2] <= DOUT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[3] <= DOUT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[4] <= DOUT[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[5] <= DOUT[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[6] <= DOUT[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[7] <= DOUT[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[8] <= DOUT[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[9] <= DOUT[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[10] <= DOUT[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[11] <= DOUT[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[12] <= DOUT[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[13] <= DOUT[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[14] <= DOUT[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[15] <= DOUT[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[16] <= DOUT[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[17] <= DOUT[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[18] <= DOUT[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[19] <= DOUT[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[20] <= DOUT[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[21] <= DOUT[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[22] <= DOUT[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[23] <= DOUT[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|SIN|SIN_ROM:u3
address[0] => lpm_rom:lpm_rom_component.address[0]
address[1] => lpm_rom:lpm_rom_component.address[1]
address[2] => lpm_rom:lpm_rom_component.address[2]
address[3] => lpm_rom:lpm_rom_component.address[3]
address[4] => lpm_rom:lpm_rom_component.address[4]
address[5] => lpm_rom:lpm_rom_component.address[5]
address[6] => lpm_rom:lpm_rom_component.address[6]
address[7] => lpm_rom:lpm_rom_component.address[7]
address[8] => lpm_rom:lpm_rom_component.address[8]
address[9] => lpm_rom:lpm_rom_component.address[9]
inclock => lpm_rom:lpm_rom_component.inclock
q[0] <= lpm_rom:lpm_rom_component.q[0]
q[1] <= lpm_rom:lpm_rom_component.q[1]
q[2] <= lpm_rom:lpm_rom_component.q[2]
q[3] <= lpm_rom:lpm_rom_component.q[3]
q[4] <= lpm_rom:lpm_rom_component.q[4]
q[5] <= lpm_rom:lpm_rom_component.q[5]
q[6] <= lpm_rom:lpm_rom_component.q[6]
q[7] <= lpm_rom:lpm_rom_component.q[7]
q[8] <= lpm_rom:lpm_rom_component.q[8]
q[9] <= lpm_rom:lpm_rom_component.q[9]


|SIN|SIN_ROM:u3|lpm_rom:lpm_rom_component
address[0] => altrom:srom.address[0]
address[1] => altrom:srom.address[1]
address[2] => altrom:srom.address[2]
address[3] => altrom:srom.address[3]
address[4] => altrom:srom.address[4]
address[5] => altrom:srom.address[5]
address[6] => altrom:srom.address[6]
address[7] => altrom:srom.address[7]
address[8] => altrom:srom.address[8]
address[9] => altrom:srom.address[9]
inclock => altrom:srom.clocki
outclock => ~NO_FANOUT~
memenab => otri[9].OE
memenab => otri[8].OE
memenab => otri[7].OE
memenab => otri[6].OE
memenab => otri[5].OE
memenab => otri[4].OE
memenab => otri[3].OE
memenab => otri[2].OE
memenab => otri[1].OE
memenab => otri[0].OE
q[0] <= otri[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= otri[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= otri[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= otri[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= otri[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= otri[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= otri[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= otri[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= otri[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= otri[9].DB_MAX_OUTPUT_PORT_TYPE


|SIN|SIN_ROM:u3|lpm_rom:lpm_rom_component|altrom:srom
address[0] => segment[0][9].WADDR
address[0] => segment[0][9].RADDR
address[0] => segment[0][8].WADDR
address[0] => segment[0][8].RADDR
address[0] => segment[0][7].WADDR
address[0] => segment[0][7].RADDR
address[0] => segment[0][6].WADDR
address[0] => segment[0][6].RADDR
address[0] => segment[0][5].WADDR
address[0] => segment[0][5].RADDR
address[0] => segment[0][4].WADDR
address[0] => segment[0][4].RADDR
address[0] => segment[0][3].WADDR
address[0] => segment[0][3].RADDR
address[0] => segment[0][2].WADDR
address[0] => segment[0][2].RADDR
address[0] => segment[0][1].WADDR
address[0] => segment[0][1].RADDR
address[0] => segment[0][0].WADDR
address[0] => segment[0][0].RADDR
address[1] => segment[0][9].WADDR1
address[1] => segment[0][9].RADDR1
address[1] => segment[0][8].WADDR1
address[1] => segment[0][8].RADDR1
address[1] => segment[0][7].WADDR1
address[1] => segment[0][7].RADDR1
address[1] => segment[0][6].WADDR1
address[1] => segment[0][6].RADDR1
address[1] => segment[0][5].WADDR1
address[1] => segment[0][5].RADDR1
address[1] => segment[0][4].WADDR1
address[1] => segment[0][4].RADDR1
address[1] => segment[0][3].WADDR1
address[1] => segment[0][3].RADDR1
address[1] => segment[0][2].WADDR1
address[1] => segment[0][2].RADDR1
address[1] => segment[0][1].WADDR1
address[1] => segment[0][1].RADDR1
address[1] => segment[0][0].WADDR1
address[1] => segment[0][0].RADDR1
address[2] => segment[0][9].WADDR2
address[2] => segment[0][9].RADDR2
address[2] => segment[0][8].WADDR2
address[2] => segment[0][8].RADDR2
address[2] => segment[0][7].WADDR2
address[2] => segment[0][7].RADDR2
address[2] => segment[0][6].WADDR2
address[2] => segment[0][6].RADDR2
address[2] => segment[0][5].WADDR2
address[2] => segment[0][5].RADDR2
address[2] => segment[0][4].WADDR2
address[2] => segment[0][4].RADDR2
address[2] => segment[0][3].WADDR2
address[2] => segment[0][3].RADDR2
address[2] => segment[0][2].WADDR2
address[2] => segment[0][2].RADDR2
address[2] => segment[0][1].WADDR2
address[2] => segment[0][1].RADDR2
address[2] => segment[0][0].WADDR2
address[2] => segment[0][0].RADDR2
address[3] => segment[0][9].WADDR3
address[3] => segment[0][9].RADDR3
address[3] => segment[0][8].WADDR3
address[3] => segment[0][8].RADDR3
address[3] => segment[0][7].WADDR3
address[3] => segment[0][7].RADDR3
address[3] => segment[0][6].WADDR3
address[3] => segment[0][6].RADDR3
address[3] => segment[0][5].WADDR3
address[3] => segment[0][5].RADDR3
address[3] => segment[0][4].WADDR3
address[3] => segment[0][4].RADDR3
address[3] => segment[0][3].WADDR3
address[3] => segment[0][3].RADDR3
address[3] => segment[0][2].WADDR3
address[3] => segment[0][2].RADDR3
address[3] => segment[0][1].WADDR3
address[3] => segment[0][1].RADDR3
address[3] => segment[0][0].WADDR3
address[3] => segment[0][0].RADDR3
address[4] => segment[0][9].WADDR4
address[4] => segment[0][9].RADDR4
address[4] => segment[0][8].WADDR4
address[4] => segment[0][8].RADDR4
address[4] => segment[0][7].WADDR4
address[4] => segment[0][7].RADDR4
address[4] => segment[0][6].WADDR4
address[4] => segment[0][6].RADDR4
address[4] => segment[0][5].WADDR4
address[4] => segment[0][5].RADDR4
address[4] => segment[0][4].WADDR4
address[4] => segment[0][4].RADDR4
address[4] => segment[0][3].WADDR4
address[4] => segment[0][3].RADDR4
address[4] => segment[0][2].WADDR4
address[4] => segment[0][2].RADDR4
address[4] => segment[0][1].WADDR4
address[4] => segment[0][1].RADDR4
address[4] => segment[0][0].WADDR4
address[4] => segment[0][0].RADDR4
address[5] => segment[0][9].WADDR5
address[5] => segment[0][9].RADDR5
address[5] => segment[0][8].WADDR5
address[5] => segment[0][8].RADDR5
address[5] => segment[0][7].WADDR5
address[5] => segment[0][7].RADDR5
address[5] => segment[0][6].WADDR5
address[5] => segment[0][6].RADDR5
address[5] => segment[0][5].WADDR5
address[5] => segment[0][5].RADDR5
address[5] => segment[0][4].WADDR5
address[5] => segment[0][4].RADDR5
address[5] => segment[0][3].WADDR5
address[5] => segment[0][3].RADDR5
address[5] => segment[0][2].WADDR5
address[5] => segment[0][2].RADDR5
address[5] => segment[0][1].WADDR5
address[5] => segment[0][1].RADDR5
address[5] => segment[0][0].WADDR5
address[5] => segment[0][0].RADDR5
address[6] => segment[0][9].WADDR6
address[6] => segment[0][9].RADDR6
address[6] => segment[0][8].WADDR6
address[6] => segment[0][8].RADDR6
address[6] => segment[0][7].WADDR6
address[6] => segment[0][7].RADDR6
address[6] => segment[0][6].WADDR6
address[6] => segment[0][6].RADDR6
address[6] => segment[0][5].WADDR6
address[6] => segment[0][5].RADDR6
address[6] => segment[0][4].WADDR6
address[6] => segment[0][4].RADDR6
address[6] => segment[0][3].WADDR6
address[6] => segment[0][3].RADDR6
address[6] => segment[0][2].WADDR6
address[6] => segment[0][2].RADDR6
address[6] => segment[0][1].WADDR6
address[6] => segment[0][1].RADDR6
address[6] => segment[0][0].WADDR6
address[6] => segment[0][0].RADDR6
address[7] => segment[0][9].WADDR7
address[7] => segment[0][9].RADDR7
address[7] => segment[0][8].WADDR7
address[7] => segment[0][8].RADDR7
address[7] => segment[0][7].WADDR7
address[7] => segment[0][7].RADDR7