usb_def.h

USB Pad test source code with SL811 usb host ic

 /* File Name :usb_def.h  */
 /* The define file used for all usb */
#define TIME_OUT        10
#define PORTA 		P1 /* RE2-RE1-RE0-RA4-RA3-RA2-RA1-RA0 */
#define PORTB 		P3 /* RB7-RB6-RB5-RA5-RB3-RB2-RB1-RB0 */
#define PORTC 		P2
#define PORTD 		P0

#define RA0		P1.0	/* RA0 */
#define RA1		P1.1	/* A0 */
#define RA2 		P1.2	/* WR */
#define RA3		P1.3	/* RD */
#define RA4		P1.4	/* DIR */
#define RE0 		P1.5	/* RA1 */
#define RE1		P1.6	/* RA2 */
#define RE2		P1.7	/* RA3 */

#define RB2		P3.0	/* 1MS */
#define RB1		P3.1	/* SOF */
#define RB0		P3.2 	/* INT */
#define RB3		P3.3	/* SEND */
#define RA5 		P3.4	/* CS */
#define RB5		P3.5	/* MODE */
#define RB6		P3.6	/* VER */
#define RB7 		P3.7	/* RSET */
#define RA3_RST         RE2
#define RA2_CLK         RE1
#define RA1_CLR         RE0
#define RA0_CLK         RA0
/*******************************************/
/*	EP 0 registers		 */
#define EP0A_CTL	0x00
#define EP0A_ADR	0x01
#define EP0A_LEN	0x02
#define EP0A_STS	0x03
#define EP0A_CNT	0x04
#define EP0B_CTL	0x08
#define EP0B_ADR	0x09
#define EP0B_LEN	0x0a
#define EP0B_STS	0x0b
#define EP0B_CNT	0x0c

/*	EP 1 registers 		*/
#define EP1A_CTL	0x10
#define EP1A_ADR	0x11
#define EP1A_LEN	0x12
#define EP1A_STS	0x13
#define EP1A_CNT	0x14

#define EP1B_CTL	0x18
#define EP1B_ADR	0x19
#define EP1B_LEN	0x1a
#define EP1B_STS	0x1b
#define EP1B_CNT	0x1c

/*	EP 2 registers 		*/
#define EP2A_CTL	0x20
#define EP2A_ADR	0x21
#define EP2A_LEN	0x22
#define EP2A_STS	0x23
#define EP2A_CNT	0x24

#define EP2B_CTL	0x28
#define EP2B_ADR	0x29
#define EP2B_LEN	0x2a
#define EP2B_STS	0x2b
#define EP2B_CNT	0x2c

/*	EP 3 registers 		*/
#define EP3A_CTL	0x30
#define EP3A_ADR	0x31
#define EP3A_LEN	0x32
#define EP3A_STS	0x33
#define EP3A_CNT	0x34

#define EP3B_CTL	0x38
#define EP3B_ADR	0x39
#define EP3B_LEN	0x3a
#define EP3B_STS	0x3b
#define EP3B_CNT	0x3c

/*	 registers for SOF 	*/
#define	SOF_CTL		EP0A_CTL
#define SOF_ADR		EP0A_ADR
#define	SOF_LEN		EP0A_LEN
#define SOF_STS		EP0A_STS
#define SOF_BUF		0xf0

/*	SL11/H control registers 	*/
#define	USB_CTL		0x5	/* control register			*/
#define INT_ENB		0x6	/* interrupt enable register 		*/
#define	USB_ADR		0x7	/* usb address register (0 for SL11H) 	*/
#define INT_STS		0xd	/* interrupt status register 		*/
#define CUR_DTS		0xe	/* current data set register (read only)*/
#define SOF_LOW		0x15	/* sof low byte register (read only) 	*/
#define SOF_HGH		0x16	/* sof high byte register (read only) 	*/
#define DMA_CNTL	0x35	/* dma total count low byte (SL11 only) */
#define DMA_CNTH	0x36	/* dma total count high byte (SL11 only)*/

/*	Bit masks for EP control registers (EPnx_CTL) 		*/
#define	EPCTL_ARM	0x1	/* allow enabled xfers 		*/
#define EPCTL_ENB	0x2	/* allow xfers to this ep 	*/
#define EPCTL_DIR	0x4	/* 0: fr host; 1: to host 	*/
#define EPCTL_NDT	0x8	/* 0: next data set 0: a; 1: b 	*/
#define EPCTL_ISO	0x10	/* isochronous mode 		*/
#define EPCTL_STL	0x20	/* send stall			*/
#define EPCTL_SEQ	0x40	/* 0: data0; 1: data1 		*/

/*	Bit masks for EP status registers (EPnx_STS)		*/
#define	EPSTS_ACK	0x1	/* transmission ack 		*/
#define EPSTS_ERR	0x2	/* transmission err		*/
#define EPSTS_TMO	0x4	/* transmission timeout 	*/
#define EPSTS_SEQ	0x8	/* data seq--0: data0; 1: data1 */
#define EPSTS_SET	0x10	/* setup packet 		*/
#define EPSTS_OVL	0x20	/* max len exceeded for recv 	*/
#define EPSTS_NAK	0x40	/* device returns nak -- SL-11H only */
#define EPSTS_STL	0x80	/* device returns stall -- SL-11H only */

/*	Bit masks for USB control register (USB_CTL) 	*/
#define CTL_ENB		0x1	/* overall enable for xfers 	*/
#define CTL_DMA		0x2	/* dma enable (SL11 only) 	*/
#define CTL_RST		0x8	/* usn engine reset (SL11H only)*/

/*	Bit masks for intp enb/sts regs (USB_INTE/USB_INTS) 	*/
#define EP0_DONE	0x1	/* ep0 done interrupt */
#define EP1_DONE	0x2	/* ep1 done interrupt */
#define EP2_DONE	0x4	/* ep2 done interrupt */
#define EP3_DONE	0x8	/* ep3 done interrupt */
#define DMA_DONE	0x10	/* dma done interrupt (SH-11 only) */
#define SOF_REVD	0x20	/* sof received interrupt */
#define RST_REVD	0x40	/* usb reset received */
#define USB_DMA		0x80	/* USB-DMA xfer in prog (SH-11 status only) */

/*	bit masks for current data set register (CUR_DTS) */
#define EP0_CDTS	0x1	/* 0: ep0a; 1: ep0b */		
#define EP1_CDTS	0x2	/* 0: ep1a; 1: ep1b */		
#define EP2_CDTS	0x4	/* 0: ep2a; 1: ep2b */		
#define EP3_CDTS	0x8	/* 0: ep3a; 1: ep3b */		

/*****************************************************************************/
	
/*	descriptor types (Ch 9.4) */
#define DEVICE          0x1
#define CONFIGURATION   0x2
#define STRING          0x3
#define INTERFACE       0x4
#define ENDPOINT        0x5

/*	PID bit patterns (Ch 8.3.1) */
#define PID_DATA0	0xc3
#define PID_DATA1	0x4b
#define PID_SETUP	0x2d
#define PID_SOF		0xa5
#define PID_IN		0x69
#define PID_OUT		0xe1
#define PID_ACK		0xd2
#define PID_NAK		0x5a
#define PID_STALL	0x1e
#define PID_PRE		0x3c
/* */
#define EP_IN           0X03
#define EP_OUT          0X07
#define EP0_BUF         0X40
#define EP1_BUF         0X60
#define EP2_BUF         0X80
#define EP_ARM          0X01
#define EP_BUF_LEN      0X40
#define DATA0           0X00
#define DATA1           0X40
#define DATA_IN         0X00
#define DATA_OUT        0X01
#define HUB_ADDR        0X01
#define DEV_ADDR        0X02
#define DEFT_ADDR       0X00