chipscope_plbv46_iba_0.vhd

XINLINX公司开发板的嵌入式源代码

-- Chipscope PLBV46 IBA Wrapper HDL file generated by chipscope_plbv46_iba_v2_1_0's TCL Generator


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library Unisim;
use Unisim.all;

entity chipscope_plbv46_iba  is
  generic (
    C_FAMILY : string := "spartan3e";
    C_DEVICE : string := "3s500e";
    C_PACKAGE : string := "fg320";
    C_SPEEDGRADE : string := "-4";
    C_PLBV46_NUM_MASTERS : integer := 2;
    C_PLBV46_NUM_SLAVES : integer := 10;
    C_PLBV46_MID_WIDTH : integer := 1;
    C_PLBV46_AWIDTH : integer := 32;
    C_PLBV46_DWIDTH : integer := 32;
    C_NUM_DATA_SAMPLES : integer := 512;
    C_MAX_SEQUENCER_LEVELS : integer := 2;
    C_ENABLE_STORAGE_QUALIFICATION : integer := 1;
    C_ENABLE_TRIGGER_OUT : integer := 0;
    C_USE_MU_1A_RST_ERR_STAT : integer := 0;
    C_USE_MU_1B_MSTR_RST_ERR_STAT : integer := 0;
    C_USE_MU_1C_TRIG_IN : integer := 0;
    C_MU_1_TRIG_IN_WIDTH : integer := 1;
    C_MU_1_TYPE_TRIG_RST_ERR_STAT : string := "basic";
    C_MU_1_CNT_W_TRIG_RST_ERR_STAT : integer := 0;
    C_MU_1_EN_STORE_TRIG_RST_ERR_STAT : integer := 1;
    C_USE_MU_2A_STD_CTL : integer := 1;
    C_USE_MU_2B_SIZE_BE : integer := 0;
    C_USE_MU_2C_TATTR : integer := 0;
    C_MU_2_NUM_GRP_CTL : integer := 1;
    C_MU_2_TYPE_GRP_CTL : string := "basic with edges";
    C_MU_2_CNT_W_GRP_CTL : integer := 0;
    C_MU_2_EN_STORE_GRP_CTL : integer := 1;
    C_USE_MU_3A_ABUS : integer := 1;
    C_USE_MU_3B_UABUS : integer := 0;
    C_MU_3_TYPE_ADDR : string := "extended";
    C_MU_3_CNT_W_ADDR : integer := 0;
    C_MU_3_EN_STORE_ADDR : integer := 1;
    C_USE_MU_4_WR_DBUS : integer := 1;
    C_MU_4_TYPE_WR_DBUS : string := "extended";
    C_MU_4_CNT_W_WR_DBUS : integer := 0;
    C_MU_4_EN_STORE_WR_DBUS : integer := 1;
    C_USE_MU_5_RD_DBUS : integer := 0;
    C_MU_5_TYPE_RD_DBUS : string := "extended with edges";
    C_MU_5_CNT_W_RD_DBUS : integer := 0;
    C_MU_5_EN_STORE_RD_DBUS : integer := 1;
    C_USE_MU_6A_SLV_CTL : integer := 0;
    C_USE_MU_6B_SLV_SZ_WADDR : integer := 0;
    C_MU_6_NUM_SLV_CTL_BUS : integer := 1;
    C_MU_6_TYPE_SLV_CTL_BUS : string := "basic with edges";
    C_MU_6_CNT_W_SLV_CTL_BUS : integer := 0;
    C_MU_6_EN_STORE_SLV_CTL_BUS : integer := 1;
    C_USE_MU_7_SLV_BSY : integer := 0;
    C_MU_7_TYPE_SLV_BSY : string := "basic with edges";
    C_MU_7_CNT_W_SLV_BSY : integer := 0;
    C_MU_7_EN_STORE_SLV_BSY : integer := 1;
    C_USE_MU_8_SLV_RD_ERR : integer := 0;
    C_MU_8_TYPE_SLV_RD_ERR : string := "basic with edges";
    C_MU_8_CNT_W_SLV_RD_ERR : integer := 0;
    C_MU_8_EN_STORE_SLV_RD_ERR : integer := 1;
    C_USE_MU_9_SLV_WR_ERR : integer := 0;
    C_MU_9_TYPE_SLV_WR_ERR : string := "basic with edges";
    C_MU_9_CNT_W_SLV_WR_ERR : integer := 0;
    C_MU_9_EN_STORE_SLV_WR_ERR : integer := 1;
    C_USE_MU_10_ARB_CTL : integer := 0;
    C_MU_10_TYPE_ARB_CTL : string := "basic with edges";
    C_MU_10_CNT_W_ARB_CTL : integer := 0;
    C_MU_10_EN_STORE_ARB_CTL : integer := 1;
    C_USE_MU_11_MSTR_CTL : integer := 0;
    C_MU_11_NUM_MSTR_CTL : integer := 1;
    C_MU_11_TYPE_MSTR_CTL : string := "basic with edges";
    C_MU_11_CNT_W_MSTR_CTL : integer := 0;
    C_MU_11_EN_STORE_MSTR_CTL : integer := 1;
    C_USE_MU_12_MSTR_SZ : integer := 0;
    C_MU_12_TYPE_MSTR_SZ : string := "basic with edges";
    C_MU_12_CNT_W_MSTR_SZ : integer := 0;
    C_MU_12_EN_STORE_MSTR_SZ : integer := 1;
    C_USE_MU_13_MSTR_BE : integer := 0;
    C_MU_13_TYPE_MSTR_BE : string := "basic with edges";
    C_MU_13_CNT_W_MSTR_BE : integer := 0;
    C_MU_13_EN_STORE_MSTR_BE : integer := 1);
 port (
    chipscope_icon_control : in  std_logic_vector(35 downto 0);
    iba_trig_out: out std_logic;
    PLB_Clk : in  std_logic;
    iba_trig_in : in std_logic_vector(0 to 0);
    PLB_Rst : in std_logic;
    Bus_Error_Det : in std_logic;
    PLB_lockErr : in std_logic;
    PLB_MRdErr : in std_logic_vector(0 to 1);
    PLB_MWrErr : in std_logic_vector(0 to 1);
    PLB_MIRQ : in std_logic_vector(0 to 1);
    PLB_MTimeout : in std_logic_vector(0 to 1);
    PLB_PAValid : in std_logic;
    PLB_SAValid : in std_logic;
    PLB_busLock : in std_logic;
    PLB_abort : in std_logic;
    PLB_Swait : in std_logic;
    PLB_SaddrAck : in std_logic;
    PLB_Srearbitrate : in std_logic;
    PLB_RNW : in std_logic;
    PLB_SwrDAck : in std_logic;
    PLB_SwrComp : in std_logic;
    PLB_SwrBTerm : in std_logic;
    PLB_wrBurst : in std_logic;
    PLB_SrdDAck : in std_logic;
    PLB_SrdComp : in std_logic;
    PLB_SrdBTerm : in std_logic;
    PLB_rdBurst : in std_logic;
    PLB_size : in std_logic_vector(0 to 3);
    PLB_type : in std_logic_vector(0 to 2);
    PLB_MSize : in std_logic_vector(0 to 1);
    PLB_Ssize : in std_logic_vector(0 to 1);
    PLB_masterID : in std_logic_vector(0 to 0);
    PLB_BE : in std_logic_vector(0 to 3);
    PLB_TAttribute : in std_logic_vector(0 to 15);
    PLB_ABus : in std_logic_vector(0 to 31);
    PLB_UABus : in std_logic_vector(0 to 31);
    PLB_wrDBus : in std_logic_vector(0 to 31);
    PLB_SrdDBus : in std_logic_vector(0 to 31);
    PLB_rdPrim : in std_logic_vector(0 to 9);
    PLB_wrPrim : in std_logic_vector(0 to 9);
    Sl_AddrAck : in std_logic_vector(0 to 9);
    Sl_Rearbitrate : in std_logic_vector(0 to 9);
    Sl_wait : in std_logic_vector(0 to 9);
    Sl_rdBTerm : in std_logic_vector(0 to 9);
    Sl_rdComp : in std_logic_vector(0 to 9);
    Sl_rdDAck : in std_logic_vector(0 to 9);
    Sl_wrBTerm : in std_logic_vector(0 to 9);
    Sl_wrComp : in std_logic_vector(0 to 9);
    Sl_wrDAck : in std_logic_vector(0 to 9);
    Sl_rdWdAddr : in std_logic_vector(0 to 39);
    Sl_SSize : in std_logic_vector(0 to 19);
    Sl_MBusy : in std_logic_vector(0 to 19);
    Sl_MRdErr : in std_logic_vector(0 to 19);
    Sl_MWrErr : in std_logic_vector(0 to 19);
    M_request : in std_logic_vector(0 to 1);
    M_priority : in std_logic_vector(0 to 3);
    M_busLock : in std_logic_vector(0 to 1);
    M_abort : in std_logic_vector(0 to 1);
    PLB_rdPenPri : in std_logic_vector(0 to 1);
    PLB_wrPenPri : in std_logic_vector(0 to 1);
    PLB_rdPenReq : in std_logic;
    PLB_wrPenReq : in std_logic;
    PLB_reqPri : in std_logic_vector(0 to 1);
    M_lockErr : in std_logic_vector(0 to 1);
    M_rdBurst : in std_logic_vector(0 to 1);
    M_wrBurst : in std_logic_vector(0 to 1);
    M_RNW : in std_logic_vector(0 to 1);
    PLB_MBusy : in std_logic_vector(0 to 1);
    PLB_MAddrAck : in std_logic_vector(0 to 1);
    PLB_MRdBTerm : in std_logic_vector(0 to 1);
    PLB_MRdDAck : in std_logic_vector(0 to 1);
    PLB_MRearbitrate : in std_logic_vector(0 to 1);
    PLB_MWrBTerm : in std_logic_vector(0 to 1);
    PLB_MWrDAck : in std_logic_vector(0 to 1);
    M_mSize : in std_logic_vector(0 to 3);
    M_size : in std_logic_vector(0 to 7);
    PLB_MSSize : in std_logic_vector(0 to 3);
    M_type : in std_logic_vector(0 to 5);
    M_BE : in std_logic_vector(0 to 7));
end entity chipscope_plbv46_iba;

-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------

architecture imp of chipscope_plbv46_iba is


-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------

  -------------------------------------------------------------------
  --
  --  IBA/PLB core component declaration
  -------------------------------------------------------------------
  component chipscope_plbv46_iba_0 is
    port (
      control : in std_logic_vector(35 downto 0);
      trig0 : in std_logic_vector(15 downto 0);
      trig1 : in std_logic_vector(31 downto 0);
      trig2 : in std_logic_vector(31 downto 0);
      clk : in std_logic);
  end component chipscope_plbv46_iba_0;

  signal trig0 : std_logic_vector(15 downto 0);
  signal trig1 : std_logic_vector(31 downto 0);
  signal trig2 : std_logic_vector(31 downto 0);

-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------

begin  -- architecture imp

  -----------------------------------------------------------------------------
  -- ILA instantiation
  -----------------------------------------------------------------------------
  i_chipscope_plbv46_iba_0 : chipscope_plbv46_iba_0
    port map
    (
      control => chipscope_icon_control,
      trig0 => trig0,
      trig1 => trig1,
      trig2 => trig2,
      clk => PLB_Clk);

  -----------------------------------------------------------------------------
  trig0(0) <= PLB_PAValid;
  trig0(1) <= PLB_SAValid;
  trig0(2) <= PLB_busLock;
  trig0(3) <= PLB_abort;
  trig0(4) <= PLB_Swait;
  trig0(5) <= PLB_SaddrAck;
  trig0(6) <= PLB_Srearbitrate;
  trig0(7) <= PLB_RNW;
  trig0(8) <= PLB_SwrDAck;
  trig0(9) <= PLB_SwrComp;
  trig0(10) <= PLB_SwrBTerm;
  trig0(11) <= PLB_wrBurst;
  trig0(12) <= PLB_SrdDAck;
  trig0(13) <= PLB_SrdComp;
  trig0(14) <= PLB_SrdBTerm;
  trig0(15) <= PLB_rdBurst;
  -----------------------------------------------------------------------------
  trig1(0) <= PLB_ABus(31);
  trig1(1) <= PLB_ABus(30);
  trig1(2) <= PLB_ABus(29);
  trig1(3) <= PLB_ABus(28);
  trig1(4) <= PLB_ABus(27);
  trig1(5) <= PLB_ABus(26);
  trig1(6) <= PLB_ABus(25);
  trig1(7) <= PLB_ABus(24);
  trig1(8) <= PLB_ABus(23);
  trig1(9) <= PLB_ABus(22);
  trig1(10) <= PLB_ABus(21);
  trig1(11) <= PLB_ABus(20);
  trig1(12) <= PLB_ABus(19);
  trig1(13) <= PLB_ABus(18);
  trig1(14) <= PLB_ABus(17);
  trig1(15) <= PLB_ABus(16);
  trig1(16) <= PLB_ABus(15);
  trig1(17) <= PLB_ABus(14);
  trig1(18) <= PLB_ABus(13);
  trig1(19) <= PLB_ABus(12);
  trig1(20) <= PLB_ABus(11);
  trig1(21) <= PLB_ABus(10);
  trig1(22) <= PLB_ABus(9);
  trig1(23) <= PLB_ABus(8);
  trig1(24) <= PLB_ABus(7);
  trig1(25) <= PLB_ABus(6);
  trig1(26) <= PLB_ABus(5);
  trig1(27) <= PLB_ABus(4);
  trig1(28) <= PLB_ABus(3);
  trig1(29) <= PLB_ABus(2);
  trig1(30) <= PLB_ABus(1);
  trig1(31) <= PLB_ABus(0);
  -----------------------------------------------------------------------------
  trig2(0) <= PLB_wrDBus(31);
  trig2(1) <= PLB_wrDBus(30);
  trig2(2) <= PLB_wrDBus(29);
  trig2(3) <= PLB_wrDBus(28);
  trig2(4) <= PLB_wrDBus(27);
  trig2(5) <= PLB_wrDBus(26);
  trig2(6) <= PLB_wrDBus(25);
  trig2(7) <= PLB_wrDBus(24);
  trig2(8) <= PLB_wrDBus(23);
  trig2(9) <= PLB_wrDBus(22);
  trig2(10) <= PLB_wrDBus(21);
  trig2(11) <= PLB_wrDBus(20);
  trig2(12) <= PLB_wrDBus(19);
  trig2(13) <= PLB_wrDBus(18);
  trig2(14) <= PLB_wrDBus(17);
  trig2(15) <= PLB_wrDBus(16);
  trig2(16) <= PLB_wrDBus(15);
  trig2(17) <= PLB_wrDBus(14);
  trig2(18) <= PLB_wrDBus(13);
  trig2(19) <= PLB_wrDBus(12);
  trig2(20) <= PLB_wrDBus(11);
  trig2(21) <= PLB_wrDBus(10);
  trig2(22) <= PLB_wrDBus(9);
  trig2(23) <= PLB_wrDBus(8);
  trig2(24) <= PLB_wrDBus(7);
  trig2(25) <= PLB_wrDBus(6);
  trig2(26) <= PLB_wrDBus(5);
  trig2(27) <= PLB_wrDBus(4);
  trig2(28) <= PLB_wrDBus(3);
  trig2(29) <= PLB_wrDBus(2);
  trig2(30) <= PLB_wrDBus(1);
  trig2(31) <= PLB_wrDBus(0);

end architecture imp;