chipscope_icon_0.xco

XINLINX公司开发板的嵌入式源代码

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#
# Xilinx Core Generator version K.34
# Date: Wed Jun 11 05:28:44 2008
#
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#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
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#
# BEGIN Project Options
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = 3s500e
SET devicefamily = spartan3e
SET flowvendor = Other
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = fg320
SET removerpms = False
SET simulationfiles = structural
SET speedgrade = -4
SET verilogsim = False
SET vhdlsim = False
# END Project Options
# BEGIN Select
SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.02.a
# END Select
# BEGIN Parameters
CSET component_name=chipscope_icon_0
CSET number_control_ports=1
CSET use_ext_bscan=true
CSET use_jtag_bufg=true
# END Parameters
GENERATE
# CRC: 2097d6fe