coregen.cgp

XINLINX公司开发板的嵌入式源代码

# Date: Wed Jun 11 05:26:25 2008
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc5vlx20t
SET devicefamily = virtex5
SET flowvendor = Other
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ff323
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = False
SET vhdlsim = True
SET workingdirectory = C:\xup\embedded\labs\lab6\implementation\chipscope_plbv46_iba_0_wrapper\tmp