csl_emifhal.h

在DSP6416T上实现的二次引导程序

    |_PER_FMK(EMIF,GBLCTL,RBTR8,rbtr8)\
  )
#endif

#if (CHIP_6713 || CHIP_DA610 || CHIP_6711C || CHIP_6712C)
  #define EMIF_GBLCTL_DEFAULT (Uint32)( \
    0x00003000\
    |_PER_FDEFAULT(EMIF,GBLCTL,BUSREQ)\
    |_PER_FDEFAULT(EMIF,GBLCTL,ARDY)\
    |_PER_FDEFAULT(EMIF,GBLCTL,HOLD)\
    |_PER_FDEFAULT(EMIF,GBLCTL,HOLDA)\
    |_PER_FDEFAULT(EMIF,GBLCTL,NOHOLD)\
    |_PER_FDEFAULT(EMIF,GBLCTL,EKEN)\
    |_PER_FDEFAULT(EMIF,GBLCTL,CLK1EN)\
    |_PER_FDEFAULT(EMIF,GBLCTL,CLK2EN)\
  )

  #define EMIF_GBLCTL_RMK(nohold,eken,clk1en,clk2en) (Uint32)( \
     _PER_FMK(EMIF,GBLCTL,NOHOLD,nohold)\
    |_PER_FMK(EMIF,GBLCTL,EKEN,eken)\
    |_PER_FMK(EMIF,GBLCTL,CLK1EN,clk1en)\
    |_PER_FMK(EMIF,GBLCTL,CLK2EN,clk2en)\
  )
#endif

  #define _EMIF_GBLCTL_FGET(FIELD)\
    _PER_FGET(_EMIF_GBLCTL_ADDR,EMIF,GBLCTL,##FIELD)

  #define _EMIF_GBLCTL_FSET(FIELD,field)\
    _PER_FSET(_EMIF_GBLCTL_ADDR,EMIF,GBLCTL,##FIELD,field)

  #define _EMIF_GBLCTL_FSETS(FIELD,SYM)\
    _PER_FSETS(_EMIF_GBLCTL_ADDR,EMIF,GBLCTL,##FIELD,##SYM)


/******************************************************************************\
* _____________________
* |                   |
* |  C E C T L        |
* |___________________|
*
* CECTL0 - CE space control register 0
* CECTL1 - CE space control register 1
* CECTL2 - CE space control register 2
* CECTL3 - CE space control register 3
*
* FIELDS (msb -> lsb)
* (rw) WRSETUP
* (rw) WRSTRB
* (rw) WRHLD
* (rw) RDSETUP
* (rw) TA       (1) 
* (rw) RDSTRB
* (rw) MTYPE
* (rw) WRHLDMSB 
* (rw) RDHLD
*
* (1) - Field only exists for C11_SUPPORT
* 
*
\******************************************************************************/
  #define _EMIF_CECTL0_OFFSET          2
  #define _EMIF_CECTL1_OFFSET          1
  #define _EMIF_CECTL2_OFFSET          4
  #define _EMIF_CECTL3_OFFSET          5

  #define _EMIF_CECTL0_ADDR            0x01800008u
  #define _EMIF_CECTL1_ADDR            0x01800004u
  #define _EMIF_CECTL2_ADDR            0x01800010u
  #define _EMIF_CECTL3_ADDR            0x01800014u

  #define _EMIF_CECTL_WRSETUP_MASK     0xF0000000u
  #define _EMIF_CECTL_WRSETUP_SHIFT    0x0000001Cu
  #define  EMIF_CECTL_WRSETUP_DEFAULT  0x0000000Fu
  #define  EMIF_CECTL_WRSETUP_OF(x)    _VALUEOF(x)

  #define _EMIF_CECTL_WRSTRB_MASK      0x0FC00000u
  #define _EMIF_CECTL_WRSTRB_SHIFT     0x00000016u
  #define  EMIF_CECTL_WRSTRB_DEFAULT   0x0000003Fu
  #define  EMIF_CECTL_WRSTRB_OF(x)     _VALUEOF(x)

  #define _EMIF_CECTL_WRHLD_MASK       0x00300000u
  #define _EMIF_CECTL_WRHLD_SHIFT      0x00000014u
  #define  EMIF_CECTL_WRHLD_DEFAULT    0x00000003u
  #define  EMIF_CECTL_WRHLD_OF(x)      _VALUEOF(x)
  
  #define _EMIF_CECTL_RDSETUP_MASK     0x000F0000u
  #define _EMIF_CECTL_RDSETUP_SHIFT    0x00000010u
  #define  EMIF_CECTL_RDSETUP_DEFAULT  0x0000000Fu
  #define  EMIF_CECTL_RDSETUP_OF(x)    _VALUEOF(x)

#if (C11_SUPPORT)
  #define _EMIF_CECTL_TA_MASK          0x0000C000u
  #define _EMIF_CECTL_TA_SHIFT         0x0000000Eu
  #define  EMIF_CECTL_TA_DEFAULT       0x00000003u
  #define  EMIF_CECTL_TA_OF(x)         _VALUEOF(x)
#endif

  #define _EMIF_CECTL_RDSTRB_MASK      0x00003F00u
  #define _EMIF_CECTL_RDSTRB_SHIFT     0x00000008u
  #define  EMIF_CECTL_RDSTRB_DEFAULT   0x0000003Fu
  #define  EMIF_CECTL_RDSTRB_OF(x)     _VALUEOF(x)
  
#if (C11_SUPPORT)
  #define _EMIF_CECTL_MTYPE_MASK       0x000000F0u
  #define _EMIF_CECTL_MTYPE_SHIFT      0x00000004u
  #define  EMIF_CECTL_MTYPE_DEFAULT    0x00000002u
  #define  EMIF_CECTL_MTYPE_OF(x)      _VALUEOF(x)
  #if (CHIP_6712 || CHIP_6712C)  /* 16-bit EMIF */ 
  #define  EMIFB_CECTL_MTYPE_ASYNC8     0x00000000u 
  #define  EMIFB_CECTL_MTYPE_ASYNC16    0x00000001u 
  #define  EMIFB_CECTL_MTYPE_SDRAM8     0x00000008u 
  #define  EMIFB_CECTL_MTYPE_SDRAM16    0x00000009u 
  #define  EMIFB_CECTL_MTYPE_SYNC8      0x0000000Au 
  #define  EMIFB_CECTL_MTYPE_SYNC16     0x0000000Bu 
  #else /* CHIP_6211/C6711/6711C 32-bit EMIF */
  #define  EMIF_CECTL_MTYPE_ASYNC8     0x00000000u
  #define  EMIF_CECTL_MTYPE_ASYNC16    0x00000001u
  #define  EMIF_CECTL_MTYPE_ASYNC32    0x00000002u
  #define  EMIF_CECTL_MTYPE_SDRAM32    0x00000003u
  #define  EMIF_CECTL_MTYPE_SBSRAM32   0x00000004u
  #define  EMIF_CECTL_MTYPE_SDRAM8     0x00000008u
  #define  EMIF_CECTL_MTYPE_SDRAM16    0x00000009u
  #define  EMIF_CECTL_MTYPE_SBSRAM8    0x0000000Au
  #define  EMIF_CECTL_MTYPE_SBSRAM16   0x0000000Bu
  #endif
 
#else
  #define _EMIF_CECTL_MTYPE_MASK       0x00000070u
  #define _EMIF_CECTL_MTYPE_SHIFT      0x00000004u
  #define  EMIF_CECTL_MTYPE_DEFAULT    0x00000002u
  #define  EMIF_CECTL_MTYPE_OF(x)      _VALUEOF(x)
  #define  EMIF_CECTL_MTYPE_ASYNC8     0x00000000u
  #define  EMIF_CECTL_MTYPE_ASYNC16    0x00000001u
  #define  EMIF_CECTL_MTYPE_ASYNC32    0x00000002u
  #define  EMIF_CECTL_MTYPE_SDRAM32    0x00000003u
  #define  EMIF_CECTL_MTYPE_SBSRAM32   0x00000004u
#endif


#if (C11_SUPPORT )
  #define _EMIF_CECTL_RDHLD_MASK       0x00000007u
  #define _EMIF_CECTL_RDHLD_SHIFT      0x00000000u
  #define  EMIF_CECTL_RDHLD_DEFAULT    0x00000003u
  #define  EMIF_CECTL_RDHLD_OF(x)      _VALUEOF(x)
#else
  #define _EMIF_CECTL_RDHLD_MASK       0x00000003u
  #define _EMIF_CECTL_RDHLD_SHIFT      0x00000000u
  #define  EMIF_CECTL_RDHLD_DEFAULT    0x00000003u
  #define  EMIF_CECTL_RDHLD_OF(x)      _VALUEOF(x)
#endif

  #define  EMIF_CECTL_OF(x)            _VALUEOF(x)

#if (C11_SUPPORT)
  #define EMIF_CECTL_DEFAULT (Uint32)( \
     _PER_FDEFAULT(EMIF,CECTL,WRSETUP)\
    |_PER_FDEFAULT(EMIF,CECTL,WRSTRB)\
    |_PER_FDEFAULT(EMIF,CECTL,WRHLD)\
    |_PER_FDEFAULT(EMIF,CECTL,RDSETUP)\
    |_PER_FDEFAULT(EMIF,CECTL,TA)\
    |_PER_FDEFAULT(EMIF,CECTL,RDSTRB)\
    |_PER_FDEFAULT(EMIF,CECTL,MTYPE)\
    |_PER_FDEFAULT(EMIF,CECTL,RDHLD)\
  )

  #define EMIF_CECTL_RMK(wrsetup,wrstrb,wrhld,rdsetup,ta,rdstrb,mtype,\
    rdhld) (Uint32)( \
     _PER_FMK(EMIF,CECTL,WRSETUP,wrsetup)\
    |_PER_FMK(EMIF,CECTL,WRSTRB,wrstrb)\
    |_PER_FMK(EMIF,CECTL,WRHLD,wrhld)\
    |_PER_FMK(EMIF,CECTL,RDSETUP,rdsetup)\
    |_PER_FMK(EMIF,CECTL,TA,ta)\
    |_PER_FMK(EMIF,CECTL,RDSTRB,rdstrb)\
    |_PER_FMK(EMIF,CECTL,MTYPE,mtype)\
    |_PER_FMK(EMIF,CECTL,RDHLD,rdhld)\
  )
#endif



#if (!C11_SUPPORT)
  #define EMIF_CECTL_DEFAULT (Uint32)( \
     _PER_FDEFAULT(EMIF,CECTL,WRSETUP)\
    |_PER_FDEFAULT(EMIF,CECTL,WRSTRB)\
    |_PER_FDEFAULT(EMIF,CECTL,WRHLD)\
    |_PER_FDEFAULT(EMIF,CECTL,RDSETUP)\
    |_PER_FDEFAULT(EMIF,CECTL,RDSTRB)\
    |_PER_FDEFAULT(EMIF,CECTL,MTYPE)\
    |_PER_FDEFAULT(EMIF,CECTL,RDHLD)\
  )

  #define EMIF_CECTL_RMK(wrsetup,wrstrb,wrhld,rdsetup,rdstrb,mtype,\
    rdhld) (Uint32)( \
     _PER_FMK(EMIF,CECTL,WRSETUP,wrsetup)\
    |_PER_FMK(EMIF,CECTL,WRSTRB,wrstrb)\
    |_PER_FMK(EMIF,CECTL,WRHLD,wrhld)\
    |_PER_FMK(EMIF,CECTL,RDSETUP,rdsetup)\
    |_PER_FMK(EMIF,CECTL,RDSTRB,rdstrb)\
    |_PER_FMK(EMIF,CECTL,MTYPE,mtype)\
    |_PER_FMK(EMIF,CECTL,RDHLD,rdhld)\
  )
#endif

  #define _EMIF_CECTL_FGET(N,FIELD)\
    _PER_FGET(_EMIF_CECTL##N##_ADDR,EMIF,CECTL,##FIELD)

  #define _EMIF_CECTL_FSET(N,FIELD,f)\
    _PER_FSET(_EMIF_CECTL##N##_ADDR,EMIF,CECTL,##FIELD,f)

  #define _EMIF_CECTL_FSETS(N,FIELD,SYM)\
    _PER_FSETS(_EMIF_CECTL##N##_ADDR,EMIF,CECTL,##FIELD,##SYM)

  #define _EMIF_CECTL0_FGET(FIELD) _EMIF_CECTL_FGET(0,##FIELD)
  #define _EMIF_CECTL1_FGET(FIELD) _EMIF_CECTL_FGET(1,##FIELD)
  #define _EMIF_CECTL2_FGET(FIELD) _EMIF_CECTL_FGET(2,##FIELD)
  #define _EMIF_CECTL3_FGET(FIELD) _EMIF_CECTL_FGET(3,##FIELD)

  #define _EMIF_CECTL0_FSET(FIELD,f) _EMIF_CECTL_FSET(0,##FIELD,f)
  #define _EMIF_CECTL1_FSET(FIELD,f) _EMIF_CECTL_FSET(1,##FIELD,f)
  #define _EMIF_CECTL2_FSET(FIELD,f) _EMIF_CECTL_FSET(2,##FIELD,f)
  #define _EMIF_CECTL3_FSET(FIELD,f) _EMIF_CECTL_FSET(3,##FIELD,f)

  #define _EMIF_CECTL0_FSETS(FIELD,SYM) _EMIF_CECTL_FSETS(0,##FIELD,##SYM)
  #define _EMIF_CECTL1_FSETS(FIELD,SYM) _EMIF_CECTL_FSETS(1,##FIELD,##SYM)
  #define _EMIF_CECTL2_FSETS(FIELD,SYM) _EMIF_CECTL_FSETS(2,##FIELD,##SYM)
  #define _EMIF_CECTL3_FSETS(FIELD,SYM) _EMIF_CECTL_FSETS(3,##FIELD,##SYM)


/******************************************************************************\
* _____________________
* |                   |
* |  S D C T L        |
* |___________________|
*
* SDCTL   - SDRAM control regsiter
*
* FIELDS (msb -> lsb)
* (rw) SDBSZ (2)
* (rw) SDRSZ (2)
* (rw) SDCSZ (2)
* (rw) SDWID (1)
* (rw) RFEN
* (r)  INIT
* (rw) TRCD
* (rw) TRP
* (rw) TRC
*
* (1) - Field only exists for C01_SUPPORT
* (2) - Field only exists for C11_SUPPORT 
*
\******************************************************************************/
  #define _EMIF_SDCTL_OFFSET           6

  #define _EMIF_SDCTL_ADDR             0x01800018u

#if (C11_SUPPORT)
  #define _EMIF_SDCTL_SDBSZ_MASK       0x40000000u
  #define _EMIF_SDCTL_SDBSZ_SHIFT      0x0000001Eu
  #define  EMIF_SDCTL_SDBSZ_DEFAULT    0x00000000u
  #define  EMIF_SDCTL_SDBSZ_OF(x)      _VALUEOF(x)
  #define  EMIF_SDCTL_SDBSZ_2BANKS     0x00000000u
  #define  EMIF_SDCTL_SDBSZ_4BANKS     0x00000001u
#endif
  
#if (C11_SUPPORT)
  #define _EMIF_SDCTL_SDRSZ_MASK       0x30000000u
  #define _EMIF_SDCTL_SDRSZ_SHIFT      0x0000001Cu
  #define  EMIF_SDCTL_SDRSZ_DEFAULT    0x00000000u
  #define  EMIF_SDCTL_SDRSZ_OF(x)      _VALUEOF(x)
  #define  EMIF_SDCTL_SDRSZ_11ROW      0x00000000u
  #define  EMIF_SDCTL_SDRSZ_12ROW      0x00000001u
  #define  EMIF_SDCTL_SDRSZ_13ROW      0x00000002u
#endif
  
#if (C11_SUPPORT)
  #define _EMIF_SDCTL_SDCSZ_MASK       0x0C000000u
  #define _EMIF_SDCTL_SDCSZ_SHIFT      0x0000001Au
  #define  EMIF_SDCTL_SDCSZ_DEFAULT    0x00000000u
  #define  EMIF_SDCTL_SDCSZ_OF(x)      _VALUEOF(x)
  #define  EMIF_SDCTL_SDCSZ_9COL       0x00000000u
  #define  EMIF_SDCTL_SDCSZ_8COL       0x00000001u
  #define  EMIF_SDCTL_SDCSZ_10COL      0x00000002u
#endif
  
#if !(C11_SUPPORT) 
  #define _EMIF_SDCTL_SDWID_MASK       0x04000000u
  #define _EMIF_SDCTL_SDWID_SHIFT      0x0000001Au
  #define  EMIF_SDCTL_SDWID_DEFAULT    0x00000000u
  #define  EMIF_SDCTL_SDWID_OF(x)      _VALUEOF(x)
  #define  EMIF_SDCTL_SDWID_4X8BIT     0x00000000u
  #define  EMIF_SDCTL_SDWID_2X16BIT    0x00000001u
#endif
  
  #define _EMIF_SDCTL_RFEN_MASK        0x02000000u
  #define _EMIF_SDCTL_RFEN_SHIFT       0x00000019u
  #define  EMIF_SDCTL_RFEN_DEFAULT     0x00000001u
  #define  EMIF_SDCTL_RFEN_OF(x)       _VALUEOF(x)
  #define  EMIF_SDCTL_RFEN_DISABLE     0x00000000u
  #define  EMIF_SDCTL_RFEN_ENABLE      0x00000001u

  #define _EMIF_SDCTL_INIT_MASK        0x01000000u
  #define _EMIF_SDCTL_INIT_SHIFT       0x00000018u
  #define  EMIF_SDCTL_INIT_DEFAULT     0x00000001u
  #define  EMIF_SDCTL_INIT_OF(x)       _VALUEOF(x)
  #define  EMIF_SDCTL_INIT_NO          0x00000000u
  #define  EMIF_SDCTL_INIT_YES         0x00000001u

#if (C11_SUPPORT)