uboot-hxd8.patch

Uboot常用的移植patches, 方便定制移植到s3c2440

+
+/* initial register set for PCF50606 in HXD8 devices */
+const u_int8_t pcf50606_initial_regs[__NUM_PCF50606_REGS] = {
+	[PCF50606_REG_OOCS] 	= 0x00,
+	/* gap */
+	[PCF50606_REG_INT1M]	= PCF50606_INT1_SECOND,
+	[PCF50606_REG_INT2M]	= PCF50606_INT2_CHGFOK |
+				  PCF50606_INT2_CHGERR |
+				  PCF50606_INT2_CHGFRDY |
+				  PCF50606_INT2_CHGPROT |
+				  PCF50606_INT2_CHGWD10S |
+				  PCF50606_INT2_CHGWDEXP,
+	[PCF50606_REG_INT3M]	= PCF50606_INT3_TSCPRES,
+	[PCF50606_REG_OOCC1] 	= PCF50606_OOCC1_RTCWAK |
+				  PCF50606_OOCC1_CHGWAK &
+				  PCF50606_OOCC1_EXTONWAK_NO_WAKEUP,
+	[PCF50606_REG_OOCC2]	= PCF50606_OOCC2_ONKEYDB_14ms |
+				  PCF50606_OOCC2_EXTONDB_14ms,
+	/* gap */
+	[PCF50606_REG_PSSC]	= 0x00,
+	[PCF50606_REG_PWROKM]	= 0x00,
+	/* gap */
+	[PCF50606_REG_DCDC1]	= 0xf0,	/* CORE_1V3: on */
+	[PCF50606_REG_DCDC2]	= 0x00,
+	[PCF50606_REG_DCDC3]	= 0x00,
+	[PCF50606_REG_DCDC4]	= 0x30, /* 1.25A */
+
+	[PCF50606_REG_DCDEC1]	= 0xe8, /* IO1_3V3: off */
+	[PCF50606_REG_DCDEC2]	= 0x00,
+
+	[PCF50606_REG_DCUDC1]	= 0x08, /* RF_3V3: off */
+	[PCF50606_REG_DCUDC2]	= 0x30, /* 1.25A current limit */
+
+	[PCF50606_REG_IOREGC]	= 0xf8, /* AUDIO_3V3: on */
+
+	[PCF50606_REG_D1REGC1]	= 0xf8, /* RC_3V3: on */
+
+	[PCF50606_REG_D2REGC1]	= 0x18, /* GPS_3V3: off */
+
+	[PCF50606_REG_D3REGC1]	= 0xf8, /* IO2_3V3: off */
+
+	[PCF50606_REG_LPREGC1]	= 0xf8, /* LCM_3V3: on */
+	[PCF50606_REG_LPREGC2]	= 0x00,
+
+	[PCF50606_REG_MBCC1]	= 0x00, /* charger unused */
+	[PCF50606_REG_MBCC2]	= 0x00,	/* unlimited charging */
+	[PCF50606_REG_MBCC3]	= 0x1a, /* 0.2*Ifast, 4.20V */
+	[PCF50606_REG_BBCC]	= 0x1f, /* 400uA */
+	[PCF50606_REG_ADCC1]	= 0x00,
+	[PCF50606_REG_ADCC2]	= 0x00,
+	/* gap */
+	[PCF50606_REG_ACDC1]	= 0x00,
+	[PCF50606_REG_BVMC]	= PCF50606_BVMC_THRSHLD_3V3,
+	[PCF50606_REG_PWMC1]	= 0x1f,	/* clock: 512 DC: 15/16*/
+	[PCF50606_REG_LEDC1]	= 0x00,
+	[PCF50606_REG_LEDC2]	= 0x00,
+	[PCF50606_REG_GPOC1]	= 0x03,	/* PWM ACTIVE */
+	[PCF50606_REG_GPOC2]	= 0x07,	/* back light pull low */
+	[PCF50606_REG_GPOC3]	= 0x00,
+	[PCF50606_REG_GPOC4]	= 0x00,
+	[PCF50606_REG_GPOC5]	= 0x00,
+};
+
+
Index: u-boot/board/hxd8/config.mk
===================================================================
--- /dev/null
+++ u-boot/board/hxd8/config.mk
@@ -0,0 +1,27 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <[e-mail]>
+# David Mueller, ELSOFT AG, <[e-mail]>
+#
+# FIC HXD8 board with S3C2440X (ARM920T) cpu
+#
+# see http://www.samsung.com/ for more information on SAMSUNG
+#
+
+CONFIG_USB_DFU_VENDOR=0x1457
+CONFIG_USB_DFU_PRODUCT=0x511a
+CONFIG_USB_DFU_REVISION=0x0110
+
+#
+# HXD81v011 or later has 1 bank of 128 MB SDRAM
+#
+# 	3000'0000 to 3800'0000
+# we load ourself to 37F8'0000
+#
+# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
+# optionally with a ramdisk at 3080'0000
+#
+# download area is 3200'0000 or 3300'0000
+
+# FIXME: TEXT_BASE = 0x37F80000
+TEXT_BASE = 0x33F80000
Index: u-boot/board/hxd8/u-boot.lds
===================================================================
--- /dev/null
+++ u-boot/board/hxd8/u-boot.lds
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <[e-mail]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm920t/start.o	(.text)
+	  cpu/arm920t/s3c24x0/nand_read.o (.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss (NOLOAD) : { *(.bss) }
+	_end = .;
+}
Index: u-boot/board/hxd8/lowlevel_foo.S
===================================================================
--- /dev/null
+++ u-boot/board/hxd8/lowlevel_foo.S
@@ -0,0 +1,87 @@
+
+_start:
+	b 	reset
+undefvec:
+	b	undefvec
+swivec:
+	b	swivec
+pabtvec:
+	b	pabtvec
+dabtvec:
+	b	dabtvec
+rsvdvec:
+	b	rsvdvec
+irqvec:
+	b	irqvec
+fiqvec:
+	b	fiqvec
+
+reset:
+	/*
+	 * set the cpu to SVC32 mode
+	 */
+	mrs	r0,cpsr
+	bic	r0,r0,#0x1f
+	orr	r0,r0,#0xd3
+	msr	cpsr,r0
+
+/* turn off the watchdog */
+#define pWTCON		0x53000000
+#define INTMSK		0x4A000008	/* Interupt-Controller base addresses */
+#define INTSUBMSK	0x4A00001C
+#define CLKDIVN	0x4C000014	/* clock divisor register */
+#define CAMDIVN	0x4C000018
+
+	ldr     r0, =pWTCON
+	mov     r1, #0x0
+	str     r1, [r0]
+
+	mov	r1, #0xffffffff
+	ldr	r0, =INTMSK
+	str	r1, [r0]
+	ldr	r1, =0x7ff
+	ldr	r0, =INTSUBMSK
+	str	r1, [r0]
+
+	/* FCLK:HCLK:PCLK = 1:3:6 */
+	ldr	r0, =CAMDIVN
+	mov	r1, #0
+	str	r1, [r0]
+
+	/* FCLK:HCLK:PCLK = 1:3:6 */
+	ldr	r0, =CLKDIVN
+	mov	r1, #7
+	str	r1, [r0]
+
+	bl	cpu_init_crit
+	ldr	r0,=TEXT_BASE
+	mov	pc, r0
+
+cpu_init_crit:
+	/*
+	 * flush v4 I/D caches
+	 */
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
+	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+
+	/*
+	 * disable MMU stuff and caches
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
+	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
+	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
+	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
+	mcr	p15, 0, r0, c1, c0, 0
+
+	/*
+	 * before relocating, we have to setup RAM timing
+	 * because memory timing is board-dependend, you will
+	 * find a lowlevel_init.S in your board directory.
+	 */
+	mov	ip, lr
+	bl	lowlevel_init
+	mov	lr, ip
+	mov	pc, lr
+
Index: u-boot/board/hxd8/lowlevel_foo.lds
===================================================================
--- /dev/null
+++ u-boot/board/hxd8/lowlevel_foo.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <[e-mail]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  lowlevel_foo.o (.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
Index: u-boot/cpu/arm920t/s3c24x0/nand.c
===================================================================
--- u-boot.orig/cpu/arm920t/s3c24x0/nand.c
+++ u-boot/cpu/arm920t/s3c24x0/nand.c
@@ -83,6 +83,59 @@
 #define	NFDATA		__REGb(NF_BASE + oNFDATA)
 #define	NFSTAT		__REGb(NF_BASE + oNFSTAT)
 
+#if defined(CONFIG_HXD8)
+static int hxd8_nand_dev_ready(struct mtd_info *mtd)
+{
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+	u_int32_t val = gpio->GPCDAT;
+
+	switch (nand_curr_device) {
+		case 0:
+			return (NFSTAT & 0x01);
+		case 1:	/* RnB 3 */
+			return ((val>>6) & 0x01);
+		case 2:	/* RnB 4 */
+			return ((val>>7) & 0x01);
+		case 3:	/* RnB 2 */
+			return  ((val>>5) & 0x01);
+		default:
+			return 0;
+	}
+}
+
+/* 4G Nand flash chip select function */
+static void hxd8_nand_select_chip(struct nand_chip *this, int chip)
+{
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+	if (chip == 0)
+		gpio->GPGDAT &=  ~(1 << 1);
+	else
+		gpio->GPGDAT |=  (1 << 1);
+
+	if (chip == 1)
+		gpio->GPADAT &=  ~(1 << 15);
+	else
+		gpio->GPADAT |= (1 << 15);
+
+	if (chip == 2)
+		gpio->GPADAT &=  ~(1 << 16);
+	else
+		gpio->GPADAT |=  (1 << 16);
+
+	if (chip == 3)
+		gpio->GPADAT &=  ~(1 << 14);
+	else
+		gpio->GPADAT |= (1 << 14);
+
+	/* UGLY: ew don't have mtd_info pointer, but know that
+	 * s3c24xx hwcontrol function does not use it for CLRNCE */
+	if (chip == -1)
+		this->hwcontrol(NULL, NAND_CTL_CLRNCE);
+	else
+		this->hwcontrol(NULL, NAND_CTL_SETNCE);
+}
+#endif
 
 static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd)
 {
@@ -210,6 +263,11 @@
 	nand->eccmode = NAND_ECC_SOFT;
 #endif
 
+#if defined(CONFIG_HXD8)
+	nand->dev_ready = hxd8_nand_dev_ready;
+	nand->select_chip = hxd8_nand_select_chip;
+#endif
+
 #ifdef CONFIG_S3C2410_NAND_BBT
 	nand->options = NAND_USE_FLASH_BBT | NAND_DONT_CREATE_BBT;
 #else