uboot-s3c2440.patch

Uboot常用的移植patches, 方便定制移植到s3c2440

+	unsigned char data;
+	unsigned long page_num;
+
+	/* FIXME: do this twice, for first and second page in block */
+
+	nand_clear_RnB();
+#if (NAND_PAGE_SIZE == 512)
+	NFCMD = NAND_CMD_READOOB; /* 0x50 */
+	NFADDR = BAD_BLOCK_OFFSET & 0xf;
+	NFADDR = (i >> 9) & 0xff;
+	NFADDR = (i >> 17) & 0xff;
+	NFADDR = (i >> 25) & 0xff;
+#elif (NAND_PAGE_SIZE == 2048)
+	page_num = i >> 11; /* addr / 2048 */
+	NFCMD = NAND_CMD_READ0;
+	NFADDR = BAD_BLOCK_OFFSET & 0xff;
+	NFADDR = (BAD_BLOCK_OFFSET >> 8) & 0xff;
+	NFADDR = page_num & 0xff;
+	NFADDR = (page_num >> 8) & 0xff;
+	NFADDR = (page_num >> 16) & 0xff;
+	NFCMD = NAND_CMD_READSTART;
+#endif
+	nand_wait();
+	data = (NFDATA & 0xff);
+	if (data != 0xff)
+		return 1;
+
+	return 0;
+}
+
+static int nand_read_page_ll(unsigned char *buf, unsigned long addr)
+{
+	unsigned short *ptr16 = (unsigned short *)buf;
+	unsigned int i, page_num;
+
+	nand_clear_RnB();
+
+	NFCMD = NAND_CMD_READ0;
+
+#if (NAND_PAGE_SIZE == 512)
+	/* Write Address */
+	NFADDR = addr & 0xff;
+	NFADDR = (addr >> 9) & 0xff;
+	NFADDR = (addr >> 17) & 0xff;
+	NFADDR = (addr >> 25) & 0xff;
+#elif (NAND_PAGE_SIZE == 2048)
+	page_num = addr >> 11; /* addr / 2048 */
+	/* Write Address */
+	NFADDR = 0;
+	NFADDR = 0;
+	NFADDR = page_num & 0xff;
+	NFADDR = (page_num >> 8) & 0xff;
+	NFADDR = (page_num >> 16) & 0xff;
+	NFCMD = NAND_CMD_READSTART;
+#else
+#error "unsupported nand page size"
+#endif
+	nand_wait();
+
+#if defined(CONFIG_S3C2410)
+	for (i = 0; i < NAND_PAGE_SIZE; i++) {
+		*buf = (NFDATA & 0xff);
+		buf++;
+	}
+#elif defined(CONFIG_S3C2440)
+	for (i = 0; i < NAND_PAGE_SIZE/2; i++) {
+		*ptr16 = NFDATA16;
+		ptr16++;
+	}
+#endif
+
+	return NAND_PAGE_SIZE;
+}
 
 /* low level nand read function */
 int nand_read_ll(unsigned char *buf, unsigned long start_addr, int size)
@@ -50,47 +161,28 @@ int nand_read_ll(unsigned char *buf, uns
 		return -1;	/* invalid alignment */
 
 	/* chip Enable */
-	NFCONF &= ~0x800;
+	nand_select();
+	nand_clear_RnB();
 	for (i=0; i<10; i++);
 
 	for (i=start_addr; i < (start_addr + size);) {
 #ifdef CONFIG_S3C2410_NAND_SKIP_BAD
-		if (start_addr % NAND_PAGE_SIZE == 0) {
-			unsigned char data;
-			NFCMD = 0x50;
-			NFADDR = 517&0xf;
-			NFADDR = (i >> 9) & 0xff;
-			NFADDR = (i >> 17) & 0xff;
-			NFADDR = (i >> 25) & 0xff;
-			wait_idle();
-			data = (NFDATA & 0xff);
-			if (data != 0xff) {
+		if (start_addr % NAND_BLOCK_SIZE == 0) {
+			if (is_bad_block(i)) {
 				/* Bad block */
-				i += NAND_PAGE_SIZE;
-				size += NAND_PAGE_SIZE;
+				i += NAND_BLOCK_SIZE;
+				size += NAND_BLOCK_SIZE;
 				continue;
 			}
 		}
 #endif
-		/* READ0 */
-		NFCMD = 0;
-
-		/* Write Address */
-		NFADDR = i & 0xff;
-		NFADDR = (i >> 9) & 0xff;
-		NFADDR = (i >> 17) & 0xff;
-		NFADDR = (i >> 25) & 0xff;
-
-		wait_idle();
-
-		for (j=0; j < NAND_SECTOR_SIZE; j++, i++) {
-			*buf = (NFDATA & 0xff);
-			buf++;
-		}
+		j = nand_read_page_ll(buf, i);
+		i += j;
+		buf += j;
 	}
 
 	/* chip Disable */
-	NFCONF |= 0x800;	/* chip disable */
+	nand_deselect();
 
 	return 0;
 }
Index: u-boot/cpu/arm920t/s3c24x0/nand.c
===================================================================
--- u-boot.orig/cpu/arm920t/s3c24x0/nand.c
+++ u-boot/cpu/arm920t/s3c24x0/nand.c
@@ -36,24 +36,54 @@
 #define __REGi(x)	(*(volatile unsigned int *)(x))
 
 #define	NF_BASE		0x4e000000
+
 #define	NFCONF		__REGi(NF_BASE + 0x0)
-#define	NFCMD		__REGb(NF_BASE + 0x4)
-#define	NFADDR		__REGb(NF_BASE + 0x8)
-#define	NFDATA		__REGb(NF_BASE + 0xc)
-#define	NFSTAT		__REGb(NF_BASE + 0x10)
+
+#if defined(CONFIG_S3C2410)
+
+#define oNFCMD		0x4
+#define	oNFADDR		0x8
+#define oNFDATA		0xc
+#define oNFSTAT		0x10
 #define NFECC0		__REGb(NF_BASE + 0x14)
 #define NFECC1		__REGb(NF_BASE + 0x15)
 #define NFECC2		__REGb(NF_BASE + 0x16)
+#define NFCONF_nFCE	(1<<11)
 
 #define S3C2410_NFCONF_EN          (1<<15)
 #define S3C2410_NFCONF_512BYTE     (1<<14)
 #define S3C2410_NFCONF_4STEP       (1<<13)
 #define S3C2410_NFCONF_INITECC     (1<<12)
-#define S3C2410_NFCONF_nFCE        (1<<11)
 #define S3C2410_NFCONF_TACLS(x)    ((x)<<8)
 #define S3C2410_NFCONF_TWRPH0(x)   ((x)<<4)
 #define S3C2410_NFCONF_TWRPH1(x)   ((x)<<0)
 
+#elif defined(CONFIG_S3C2440)
+
+#define oNFCMD		0x8
+#define oNFADDR		0xc
+#define oNFDATA		0x10
+#define oNFSTAT		0x20
+
+#define	NFCONT		__REGi(NF_BASE + 0x04)
+#define	NFMECC0		__REGi(NF_BASE + 0x2C)
+#define NFCONF_nFCE	(1<<1)
+#define S3C2440_NFCONF_INITECC		(1<<4)
+#define S3C2440_NFCONF_MAINECCLOCK	(1<<5)
+#define nand_select()		(NFCONT &= ~(1 << 1))
+#define nand_deselect()		(NFCONT |= (1 << 1))
+#define nand_clear_RnB()	(NFSTAT |= (1 << 2))
+#define nand_detect_RB()	{ while(!(NFSTAT&(1<<2))); }
+#define nand_wait()		{ while(!(NFSTAT & 0x4)); } /* RnB_TransDectect */
+
+#endif
+
+#define	NFCMD		__REGb(NF_BASE + oNFCMD)
+#define	NFADDR		__REGb(NF_BASE + oNFADDR)
+#define	NFDATA		__REGb(NF_BASE + oNFDATA)
+#define	NFSTAT		__REGb(NF_BASE + oNFSTAT)
+
+
 static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd)
 {
 	struct nand_chip *chip = mtd->priv;
@@ -62,23 +92,31 @@ static void s3c2410_hwcontrol(struct mtd
 
 	switch (cmd) {
 	case NAND_CTL_SETNCE:
-		NFCONF &= ~S3C2410_NFCONF_nFCE;
+#if defined(CONFIG_S3C2410)
+		NFCONF &= ~NFCONF_nFCE;
+#elif defined(CONFIG_S3C2440)
+		NFCONT &= ~NFCONF_nFCE;
+#endif
 		DEBUGN("NFCONF=0x%08x\n", NFCONF);
 		break;
 	case NAND_CTL_CLRNCE:
-		NFCONF |= S3C2410_NFCONF_nFCE;
+#if defined(CONFIG_S3C2410)
+		NFCONF |= NFCONF_nFCE;
+#elif defined(CONFIG_S3C2440)
+		NFCONT &= ~NFCONF_nFCE;
+#endif
 		DEBUGN("NFCONF=0x%08x\n", NFCONF);
 		break;
 	case NAND_CTL_SETALE:
-		chip->IO_ADDR_W = NF_BASE + 0x8;
+		chip->IO_ADDR_W = NF_BASE + oNFADDR;
 		DEBUGN("SETALE\n");
 		break;
 	case NAND_CTL_SETCLE:
-		chip->IO_ADDR_W = NF_BASE + 0x4;
+		chip->IO_ADDR_W = NF_BASE + oNFCMD;
 		DEBUGN("SETCLE\n");
 		break;
 	default:
-		chip->IO_ADDR_W = NF_BASE + 0xc;
+		chip->IO_ADDR_W = NF_BASE + oNFDATA;
 		break;
 	}
 	return;
@@ -137,15 +175,21 @@ int __board_nand_init(struct nand_chip *
 	/* initialize hardware */
 	twrph0 = 3; twrph1 = 0; tacls = 0;
 
+#if defined(CONFIG_S3C2410)
 	cfg = S3C2410_NFCONF_EN;
 	cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
 	cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
 	cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
 
 	NFCONF = cfg;
+#elif defined(CONFIG_S3C2440)
+	twrph0 = 7; twrph1 = 7; tacls = 7;
+	NFCONF = (tacls<<12)|(twrph0<<8)|(twrph1<<4)|(0<<0);
+	NFCONT = (0<<13)|(0<<12)|(0<<10)|(0<<9)|(0<<8)|(1<<6)|(1<<5)|(1<<4)|(1<<1)|(1<<0);
+#endif
 
 	/* initialize nand_chip data structure */
-	nand->IO_ADDR_R = nand->IO_ADDR_W = 0x4e00000c;
+	nand->IO_ADDR_R = nand->IO_ADDR_W = NF_BASE + oNFDATA;
 
 	/* read_buf and write_buf are default */
 	/* read_byte and write_byte are default */
@@ -170,12 +214,23 @@ int __board_nand_init(struct nand_chip *
 	nand->options = 0;
 #endif
 
+#if defined(CONFIG_S3C2440)
+/*
+	nand_select();
+	nand_clear_RnB();
+	NFCMD = NAND_CMD_RESET;
+	{ volatile int i; for (i = 0; i < 10; i ++); }
+	nand_detect_RB();
+	nand_deselect();
+*/
+#endif
+
 	DEBUGN("end of nand_init\n");
 
 	return 0;
 }
 
 #else
- #error "U-Boot legacy NAND support not available for S3C2410"
+ #error "U-Boot legacy NAND support not available for S3C24xx"
 #endif
 #endif
Index: u-boot/cpu/arm920t/s3c24x0/mmc.c
===================================================================
--- u-boot.orig/cpu/arm920t/s3c24x0/mmc.c
+++ u-boot/cpu/arm920t/s3c24x0/mmc.c
@@ -137,6 +137,9 @@ static int mmc_block_read(uchar *dst, ul
 	dcon |= S3C2410_SDIDCON_RXAFTERCMD|S3C2410_SDIDCON_XFER_RXSTART;
 	if (wide)
 		dcon |= S3C2410_SDIDCON_WIDEBUS;
+#if defined(CONFIG_S3C2440)
+	dcon |= S3C2440_SDIDCON_DS_WORD | S3C2440_SDIDCON_DATSTART;
+#endif
 	sdi->SDIDCON = dcon;
 
 	/* send read command */
@@ -394,13 +397,18 @@ int mmc_init(int verbose)
 
 	clk_power->CLKCON |= (1 << 9);
 
+	sdi->SDIBSIZE = 512;
+#if defined(CONFIG_S3C2410)
 	/* S3C2410 has some bug that prevents reliable operation at higher speed */
 	//sdi->SDIPRE = 0x3e;  /* SDCLK = PCLK/2 / (SDIPRE+1) = 396kHz */
-	sdi->SDIPRE = 0x02;  /* SDCLK = PCLK/2 / (SDIPRE+1) = 396kHz */
-	sdi->SDIBSIZE = 512;
+	sdi->SDIPRE = 0x02;  /* 2410: SDCLK = PCLK/2 / (SDIPRE+1) = 11MHz */
 	sdi->SDIDTIMER = 0xffff;
+#elif defined(CONFIG_S3C2440)
+	sdi->SDIPRE = 0x05;  /* 2410: SDCLK = PCLK / (SDIPRE+1) = 11MHz */
+	sdi->SDIDTIMER = 0x7fffff;
+#endif
 	sdi->SDIIMSK = 0x0;
-	sdi->SDICON = S3C2410_SDICON_FIFORESET|S3C2440_SDICON_MMCCLOCK;
+	sdi->SDICON = S3C2410_SDICON_FIFORESET|S3C2410_SDICON_CLOCKTYPE;
 	udelay(125000); /* FIXME: 74 SDCLK cycles */
 
 	mmc_csd.c_size = 0;
Index: u-boot/cpu/arm920t/s3c24x0/usb.c
===================================================================
--- u-boot.orig/cpu/arm920t/s3c24x0/usb.c
+++ u-boot/cpu/arm920t/s3c24x0/usb.c
@@ -24,12 +24,14 @@
 #include <common.h>
 
 #if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT)
-# if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
+# if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
 
 #if defined(CONFIG_S3C2400)
 # include <s3c2400.h>
 #elif defined(CONFIG_S3C2410)
 # include <s3c2410.h>
+#elif defined(CONFIG_S3C2440)
+# include <s3c2440.h>
 #endif
 
 int usb_cpu_init (void)
@@ -68,5 +70,5 @@ int usb_cpu_init_fail (void)
 	return 0;
 }
 
-# endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) */
+# endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) */
 #endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */
Index: u-boot/drivers/usb/usb_ohci.c
===================================================================
--- u-boot.orig/drivers/usb/usb_ohci.c
+++ u-boot/drivers/usb/usb_ohci.c
@@ -66,6 +66,7 @@
 #if defined(CONFIG_ARM920T) || \
     defined(CONFIG_S3C2400) || \
     defined(CONFIG_S3C2410) || \
+    defined(CONFIG_S3C2440) || \
     defined(CONFIG_440EP) || \
     defined(CONFIG_PCI_OHCI) || \
     defined(CONFIG_MPC5200)
Index: u-boot/cpu/arm920t/s3c24x0/cmd_s3c24xx.c
===================================================================
--- u-boot.orig/cpu/arm920t/s3c24x0/cmd_s3c24xx.c
+++ u-boot/cpu/arm920t/s3c24x0/cmd_s3c24xx.c
@@ -27,7 +27,11 @@
 #include <common.h>
 #include <command.h>
 #include <net.h>		/* for print_IPaddr */
+#if defined(CONFIG_S3C2410)
 #include <s3c2410.h>
+#elif defined(CONFIG_S3C2440)
+#include <s3c2440.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -46,6 +50,7 @@ struct s3c24x0_pll_speed {
 	u_int16_t	mhz;
 	u_int32_t	mpllcon;
 	u_int32_t	clkdivn;
+	u_int32_t	camdivn;
 };
 
 #define CLKDIVN_1_1_1	0x00
@@ -53,6 +58,11 @@ struct s3c24x0_pll_speed {
 #define CLKDIVN_1_2_4	0x03
 #define CLKDIVN_1_4_4	0x04
 
+#if defined(CONFIG_S3C2440)
+#define CLKDIVN_1_4_8	0x05
+#define CLKDIVN_1_3_6	0x07
+#endif
+
 #if defined(CONFIG_S3C2410)
 static const u_int32_t upllcon = ((0x78 << 12) + (0x2 << 4) + 0x3);
 static const struct s3c24x0_pll_speed pll_configs[] = {
@@ -77,6 +87,61 @@ static const struct s3c24x0_pll_speed pl
 		.clkdivn = CLKDIVN_1_2_4,
 	},
 };
+#elif defined(CONFIG_S3C2440)
+/* from page 7-21 of S3C2440A user's manual Revision 1 */
+#if (CONFIG_SYS_CLK_FREQ == 12000000)
+static const u_int32_t upllcon = ((0x38 << 12) + (2 << 4) + 2);
+static const struct s3c24x0_pll_speed pll_configs[] = {
+	{
+		.mhz = 200,
+		.mpllcon = ((142 << 12) + (7 << 4) + 1),
+		.clkdivn = CLKDIVN_1_2_4,
+	},
+	{
+		.mhz = 271,
+		.mpllcon = ((0xad << 12) + (0x2 << 4) + 0x2),
+		.clkdivn = CLKDIVN_1_2_4,
+	},
+	{
+		.mhz = 304,
+		.mpllcon = ((0x7d << 12) + (0x1 << 4) + 0x1),
+		.clkdivn = CLKDIVN_1_3_6,
+	},
+	{
+		.mhz = 405,
+		.mpllcon = ((0x7f << 12) + (0x2 << 4) + 0x1),
+		.clkdivn = CLKDIVN_1_3_6,
+	},
+#elif (CONFIG_SYS_CLK_FREQ == 16934400)
+static const u_int32_t upllcon = ((0x3c << 12) + (2 << 4) + 2);
+static const struct s3c24x0_pll_speed pll_configs[] = {
+	{
+		.mhz = 200,
+		.mpllcon = ((181 << 12) + (14 << 4) + 1),
+		.clkdivn = CLKDIVN_1_2_4,
+	},
+	{
+		.mhz = 266,
+		.mpllcon = ((0x76 << 12) + (0x2 << 4) + 0x2),
+		.clkdivn = CLKDIVN_1_2_4,
+		.camdivn = 0,
+	},
+	{
+		.mhz = 296,
+		.mpllcon = ((0x61 << 12) + (0x1 << 4) + 0x2),
+		.clkdivn = CLKDIVN_1_3_6,
+		.camdivn = 0,
+	},
+	{
+		.mhz = 399,
+		.mpllcon = ((0x6e << 12) + (0x3 << 4) + 0x1),
+		.clkdivn = CLKDIVN_1_3_6,
+		.camdivn = 0,
+	},
+#else
+#error "clock frequencies != 12MHz / 16.9344MHz not supported"
+#endif
+};
 #else
 #error "please define valid pll configurations for your cpu type"
 #endif
@@ -95,6 +160,10 @@ static int reconfig_mpll(u_int16_t mhz)
 
 	for (i = 0; i < ARRAY_SIZE(pll_configs); i++) {
 		if (pll_configs[i].mhz == mhz) {
+#if defined(CONFIG_S3C2440)
+			clk_power->CAMDIVN &= ~0x30;
+			clk_power->CAMDIVN |= pll_configs[i].camdivn;
+#endif
 			/* to reduce PLL lock time, adjust the LOCKTIME register */
 			clk_power->LOCKTIME = 0xFFFFFF;
 
Index: u-boot/common/serial.c
===================================================================
--- u-boot.orig/common/serial.c
+++ u-boot/common/serial.c
@@ -60,7 +60,7 @@ struct serial_device *__default_serial_c
 #else
 		return &serial0_device;
 #endif
-#elif defined(CONFIG_S3C2410)
+#elif defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
 #if defined(CONFIG_SERIAL1)
 	return &s3c24xx_serial0_device;
 #elif defined(CONFIG_SERIAL2)
@@ -133,7 +133,7 @@ void serial_initialize (void)
 #if defined (CONFIG_STUART)
 	serial_register(&serial_stuart_device);
 #endif
-#if defined(CONFIG_S3C2410)
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
 	serial_register(&s3c24xx_serial0_device);
 	serial_register(&s3c24xx_serial1_device);
 	serial_register(&s3c24xx_serial2_device);
Index: u-boot/include/serial.h
===================================================================
--- u-boot.orig/include/serial.h
+++ u-boot/include/serial.h
@@ -36,7 +36,7 @@ extern struct serial_device eserial4_dev
 
 #endif
 
-#if defined(CONFIG_S3C2410)
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
 extern struct serial_device s3c24xx_serial0_device;
 extern struct serial_device s3c24xx_serial1_device;
 extern struct serial_device s3c24xx_serial2_device;