uboot-s3c2440.patch

Uboot常用的移植patches, 方便定制移植到s3c2440

+#include <s3c2440.h>
 #endif
 
 #include <malloc.h>
Index: u-boot/cpu/arm920t/s3c24x0/speed.c
===================================================================
--- u-boot.orig/cpu/arm920t/s3c24x0/speed.c
+++ u-boot/cpu/arm920t/s3c24x0/speed.c
@@ -30,12 +30,15 @@
  */
 
 #include <common.h>
-#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
+#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || \
+    defined (CONFIG_S3C2440) || defined (CONFIG_TRAB)
 
 #if defined(CONFIG_S3C2400)
 #include <s3c2400.h>
 #elif defined(CONFIG_S3C2410)
 #include <s3c2410.h>
+#elif defined(CONFIG_S3C2440)
+#include <s3c2440.h>
 #endif
 
 #define MPLL 0
@@ -66,8 +69,17 @@ static ulong get_PLLCLK(int pllreg)
     m = ((r & 0xFF000) >> 12) + 8;
     p = ((r & 0x003F0) >> 4) + 2;
     s = r & 0x3;
-
+#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
     return((CONFIG_SYS_CLK_FREQ * m) / (p << s));
+#elif defined(CONFIG_S3C2440)
+    /* To avoid integer overflow, changed the calc order */
+    if (pllreg == MPLL)
+    	return ( 2 * m * (CONFIG_SYS_CLK_FREQ / (p << s )) );
+    else
+    	return ( m * (CONFIG_SYS_CLK_FREQ / (p << s )) );
+#else
+#error "get_PLLCLK not implemented for CPU type"
+#endif
 }
 
 /* return FCLK frequency */
@@ -81,7 +93,23 @@ ulong get_HCLK(void)
 {
     S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
 
+#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
     return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK());
+#elif defined(CONFIG_S3C2440)
+    switch (clk_power->CLKDIVN & 0x6) {
+        case 0x0:
+	    return get_FCLK();
+	case 0x2:
+	    return get_FCLK()/2;
+	case 0x4:
+	    return (clk_power->CAMDIVN & 0x200) ? get_FCLK()/8 : get_FCLK()/4;
+	case 0x6:
+	    return (clk_power->CAMDIVN & 0x100) ? get_FCLK()/6 : get_FCLK()/3;
+    }
+    return 0;
+#else
+#error "get_HCLK not implemented for CPU type"
+#endif
 }
 
 /* return PCLK frequency */
@@ -98,4 +126,5 @@ ulong get_UCLK(void)
     return(get_PLLCLK(UPLL));
 }
 
-#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
+#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) ||
+          defined(CONFIG_S3C2440) || defined (CONFIG_TRAB) */
Index: u-boot/cpu/arm920t/s3c24x0/interrupts.c
===================================================================
--- u-boot.orig/cpu/arm920t/s3c24x0/interrupts.c
+++ u-boot/cpu/arm920t/s3c24x0/interrupts.c
@@ -30,13 +30,16 @@
  */
 
 #include <common.h>
-#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
+#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || \
+    defined(CONFIG_S3C2440) || defined (CONFIG_TRAB)
 
 #include <arm920t.h>
 #if defined(CONFIG_S3C2400)
 #include <s3c2400.h>
 #elif defined(CONFIG_S3C2410)
 #include <s3c2410.h>
+#elif defined(CONFIG_S3C2440)
+#include <s3c2440.h>
 #endif
 
 int timer_load_val = 0;
@@ -59,6 +62,7 @@ int interrupt_init (void)
 	/* use PWM Timer 4 because it has no output */
 	/* prescaler for Timer 4 is 16 */
 	timers->TCFG0 = 0x0f00;
+#ifndef CONFIG_S3C2440
 	if (timer_load_val == 0)
 	{
 		/*
@@ -68,6 +72,9 @@ int interrupt_init (void)
 		 */
 		timer_load_val = get_PCLK()/(2 * 16 * 100);
 	}
+#else
+	timer_load_val = get_PCLK()/(2 * 16 * 100);
+#endif
 	/* load value for 10 ms timeout */
 	lastdec = timers->TCNTB4 = timer_load_val;
 	/* auto load, manual update of Timer 4 */
@@ -178,6 +185,7 @@ ulong get_tbclk (void)
 	tbclk = timer_load_val * 100;
 #elif defined(CONFIG_SBC2410X) || \
       defined(CONFIG_SMDK2410) || \
+      defined(CONFIG_SMDK2440) || \
       defined(CONFIG_VCMA9)
 	tbclk = CFG_HZ;
 #else
@@ -232,4 +240,5 @@ void s3c2410_irq(void)
 }
 #endif /* USE_IRQ */
 
-#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
+#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) ||
+	  defined(CONFIG_S3C2440) || defined (CONFIG_TRAB) */
Index: u-boot/cpu/arm920t/s3c24x0/serial.c
===================================================================
--- u-boot.orig/cpu/arm920t/s3c24x0/serial.c
+++ u-boot/cpu/arm920t/s3c24x0/serial.c
@@ -19,12 +19,15 @@
  */
 
 #include <common.h>
-#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
+#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || \
+    defined(CONFIG_S3C2440) || defined (CONFIG_TRAB)
 
 #if defined(CONFIG_S3C2400) || defined(CONFIG_TRAB)
 #include <s3c2400.h>
 #elif defined(CONFIG_S3C2410)
 #include <s3c2410.h>
+#elif defined(CONFIG_S3C2440)
+#include <s3c2440.h>
 #endif
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -301,4 +304,5 @@ struct serial_device s3c24xx_serial2_dev
 
 #endif /* CONFIG_SERIAL_MULTI */
 
-#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
+#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) ||
+	  defined(CONFIG_S3C2440) || defined (CONFIG_TRAB) */
Index: u-boot/cpu/arm920t/s3c24x0/i2c.c
===================================================================
--- u-boot.orig/cpu/arm920t/s3c24x0/i2c.c
+++ u-boot/cpu/arm920t/s3c24x0/i2c.c
@@ -34,6 +34,8 @@
 #include <s3c2400.h>
 #elif defined(CONFIG_S3C2410)
 #include <s3c2410.h>
+#elif defined(CONFIG_S3C2440)
+#include <s3c2440.h>
 #endif
 #include <i2c.h>
 
@@ -63,7 +65,7 @@ static int GetI2CSDA(void)
 {
 	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
 
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
 	return (gpio->GPEDAT & 0x8000) >> 15;
 #endif
 #ifdef CONFIG_S3C2400
@@ -82,7 +84,7 @@ static void SetI2CSCL(int x)
 {
 	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
 
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
 	gpio->GPEDAT = (gpio->GPEDAT & ~0x4000) | (x&1) << 14;
 #endif
 #ifdef CONFIG_S3C2400
@@ -139,7 +141,7 @@ void i2c_init (int speed, int slaveadd)
 	}
 
 	if ((status & I2CSTAT_BSY) || GetI2CSDA () == 0) {
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
 		ulong old_gpecon = gpio->GPECON;
 #endif
 #ifdef CONFIG_S3C2400
@@ -147,7 +149,7 @@ void i2c_init (int speed, int slaveadd)
 #endif
 		/* bus still busy probably by (most) previously interrupted transfer */
 
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
 		/* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
 		gpio->GPECON = (gpio->GPECON & ~0xF0000000) | 0x10000000;
 #endif
@@ -171,7 +173,7 @@ void i2c_init (int speed, int slaveadd)
 		udelay (1000);
 
 		/* restore pin functions */
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
 		gpio->GPECON = old_gpecon;
 #endif
 #ifdef CONFIG_S3C2400
Index: u-boot/drivers/usb/usbdcore_s3c2410.c
===================================================================
--- u-boot.orig/drivers/usb/usbdcore_s3c2410.c
+++ u-boot/drivers/usb/usbdcore_s3c2410.c
@@ -24,7 +24,7 @@
 
 #include <config.h>
 
-#if defined(CONFIG_S3C2410) && defined(CONFIG_USB_DEVICE)
+#if (defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)) && defined(CONFIG_USB_DEVICE)
 
 #include <common.h>
 
Index: u-boot/drivers/serial/usbtty.h
===================================================================
--- u-boot.orig/drivers/serial/usbtty.h
+++ u-boot/drivers/serial/usbtty.h
@@ -29,7 +29,7 @@
 #include "usbdcore_mpc8xx.h"
 #elif defined(CONFIG_OMAP1510)
 #include "usbdcore_omap1510.h"
-#elif defined(CONFIG_S3C2410)
+#elif defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
 #include "usbdcore_s3c2410.h"
 #endif
 
Index: u-boot/cpu/arm920t/start.S
===================================================================
--- u-boot.orig/cpu/arm920t/start.S
+++ u-boot/cpu/arm920t/start.S
@@ -31,7 +31,11 @@
 
 #include <config.h>
 #include <version.h>
+#if defined(CONFIG_S3C2410)
 #include <s3c2410.h>
+#elif defined(CONFIG_S3C2440)
+#include <s3c2440.h>
+#endif
 #include <status_led.h>
 
 /*
@@ -166,20 +170,38 @@ copyex:
 	bne	copyex
 #endif
 
-#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
+#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
 	/* turn off the watchdog */
 
 # if defined(CONFIG_S3C2400)
 #  define pWTCON		0x15300000
 #  define INTMSK		0x14400008	/* Interupt-Controller base addresses */
 #  define CLKDIVN	0x14800014	/* clock divisor register */
-#else
+#elif defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
 #  define pWTCON		0x53000000
 #  define INTMSK		0x4A000008	/* Interupt-Controller base addresses */
 #  define INTSUBMSK	0x4A00001C
 #  define CLKDIVN	0x4C000014	/* clock divisor register */
 # endif
 
+#if defined(CONFIG_S3C2410)
+# define INTSUBMSK_val	0x7ff
+# define MPLLCON_val	((0x90 << 12) + (0x7 << 4) + 0x0)	/* 202 MHz */
+# define UPLLCON_val	((0x78 << 12) + (0x2 << 4) + 0x3)
+# define CLKDIVN_val	3 /* FCLK:HCLK:PCLK = 1:2:4 */
+#elif defined(CONFIG_S3C2440)
+# define INTSUBMSK_val	0xffff
+#if (CONFIG_SYS_CLK_FREQ == 16934400)
+# define MPLLCON_val	((0x61 << 12) + (0x1 << 4) + 0x2)	/* 296.35 MHz */
+# define UPLLCON_val	((0x3c << 12) + (0x4 << 4) + 0x2)	/*  47.98 MHz */
+#else if (CONFIG_SYS_CLK_FREQ == 12000000)
+# define MPLLCON_val	((0x44 << 12) + (0x1 << 4) + 0x1)	/* 304.00 MHz */
+# define UPLLCON_val	((0x38 << 12) + (0x2 << 4) + 0x2)	/*  48.00 MHz */
+#endif
+# define CLKDIVN_val	7 /* FCLK:HCLK:PCLK = 1:3:6 */
+# define CAMDIVN	0x4C000018
+#endif
+
 	ldr     r0, =pWTCON
 	mov     r1, #0x0
 	str     r1, [r0]
@@ -190,24 +212,34 @@ copyex:
 	mov	r1, #0xffffffff
 	ldr	r0, =INTMSK
 	str	r1, [r0]
-# if defined(CONFIG_S3C2410)
-	ldr	r1, =0x3ff
+# if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+	ldr	r1, =INTSUBMSK_val
 	ldr	r0, =INTSUBMSK
 	str	r1, [r0]
 # endif
 
-	/* default FCLK is 202 MHz ! */
+#if defined(CONFIG_S3C2440)
+	/* Make sure we get FCLK:HCLK:PCLK = 1:3:6 */
+	ldr	r0, =CAMDIVN
+	mov	r1, #0
+	str	r1, [r0]
+#endif
+
+	/* Clock asynchronous mode */
+	mrc	p15, 0, r1, c1, c0, 0
+	orr	r1, r1, #0xc0000000
+	mcr	p15, 0, r1, c1, c0, 0
+
+
 #define LOCKTIME	0x4c000000
 #define UPLLCON		0x4c000008
-//#define MPLLCFG		((0x90 << 12) + (0x2 << 4) + 0x2)
-#define MPLLCFG		((0x90 << 12) + (0x7 << 4) + 0x0)
-#define UPLLCFG		((0x78 << 12) + (0x2 << 4) + 0x3)
+
 	ldr	r0, =LOCKTIME
 	mov	r1, #0xffffff
 	str	r1, [r0]
 
 	ldr	r0, =UPLLCON
-	ldr	r1, =UPLLCFG
+	ldr	r1, =UPLLCON_val
 	str	r1, [r0]
 
 	/* Page 7-19, seven nops between UPLL and MPLL */
@@ -219,12 +251,12 @@ copyex:
 	nop
 	nop
 
-	ldr	r1, =MPLLCFG
+	ldr	r1, =MPLLCON_val
 	str	r1, [r0, #-4]		/* MPLLCON */
 
 	/* FCLK:HCLK:PCLK = 1:2:4 */
 	ldr	r0, =CLKDIVN
-	mov	r1, #3
+	mov	r1, #CLKDIVN_val
 	str	r1, [r0]
 
 #if 1
@@ -252,14 +284,15 @@ copyex:
 	str	r1, [r0, #0x28]
 #endif
 
-#endif	/* CONFIG_S3C2400 || CONFIG_S3C2410 */
+#endif	/* CONFIG_S3C2400 || CONFIG_S3C2410 || CONFIG_S3C2440 */
 
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 #ifndef CONFIG_LL_INIT_NAND_ONLY
 	bl	cpu_init_crit
 #endif
 
-#if defined(CONFIG_AT91RM9200) || defined(CONFIG_S3C2410)
+#if defined(CONFIG_AT91RM9200) || defined(CONFIG_S3C2410) || \
+    defined(CONFIG_S3C2440)
 
 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
 	adr	r0, _start		/* r0 <- current position of code   */
@@ -305,6 +338,7 @@ nand_load:
 	bl	may_resume		/* low-level setup and resume */
 
 	@ reset NAND
+#if defined(CONFIG_S3C2410)
 	mov	r1, #S3C2410_NAND_BASE
 	ldr	r2, =0xf842		@ initial value enable tacls=3,rph0=6,rph1=0
 	str	r2, [r1, #oNFCONF]
@@ -323,6 +357,17 @@ nand_load:
 	ldr	r2, [r1, #oNFCONF]
 	orr	r2, r2, #0x800		@ disable chip
 	str	r2, [r1, #oNFCONF]
+#elif defined(CONFIG_S3C2440)
+	mov	r1, #S3C2440_NAND_BASE
+	ldr	r2, =0xfff0		@ initial value tacls=3,rph0=7,rph1=7
+	ldr	r3, [r1, #oNFCONF]
+	orr	r3, r3, r2
+	str	r3, [r1, #oNFCONF]
+
+	ldr	r3, [r1, #oNFCONT]
+	orr	r3, r3, #1		@ enable nand controller
+	str	r3, [r1, #oNFCONT]
+#endif /* CONFIG_S3C2440 */
 
 	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
 	sub	r0, r0, #CFG_MALLOC_LEN	/* malloc area                      */
@@ -385,7 +430,7 @@ done_nand_read:
 #endif /* CONFIG_S3C2410_NAND_BOOT */
 done_relocate:
 
-#if defined(CONFIG_USE_IRQ) && defined(CONFIG_S3C2410)
+#if defined(CONFIG_USE_IRQ) && (defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440))
 	/* In the case of the S3C2410, if we've somehow magically (JTAG, ...)
 	   ended up in RAM, then that ram is mapped to 0x30000000 and not 0.
 	   So we need to copy the interrupt vectors, etc.  */
@@ -502,7 +547,7 @@ may_resume:
 #if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && defined(CONFIG_LL_INIT_NAND_ONLY)
 	bl	cpu_init_crit
 #endif
-#if defined(CONFIG_S3C2410)
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
 	/* ensure some refresh has happened */
 	ldr	r1, =0xfffff
 1:	subs	r1, r1, #1
@@ -513,7 +558,7 @@ may_resume:
 	ldr	r0, [ r1 ]
 	tst	r0, #0x02		/* is this resume from power down */
 	ldrne	pc, [r1, #4]		/* gstatus3 */
-#endif /* CONFIG_S3C2410 */
+#endif /* CONFIG_S3C2410 || CONFIG_S3C244 */
 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
 
 	mov	pc, r10
Index: u-boot/cpu/arm920t/s3c24x0/nand_read.c
===================================================================
--- u-boot.orig/cpu/arm920t/s3c24x0/nand_read.c
+++ u-boot/cpu/arm920t/s3c24x0/nand_read.c
@@ -16,30 +16,141 @@
  */
 
 #include <common.h>
+#include <linux/mtd/nand.h>
 
 #ifdef CONFIG_S3C2410_NAND_BOOT
 
 #define __REGb(x)	(*(volatile unsigned char *)(x))
+#define __REGw(x)	(*(volatile unsigned short *)(x))
 #define __REGi(x)	(*(volatile unsigned int *)(x))
 #define NF_BASE		0x4e000000
+#if defined(CONFIG_S3C2410)
 #define NFCONF		__REGi(NF_BASE + 0x0)
 #define NFCMD		__REGb(NF_BASE + 0x4)
 #define NFADDR		__REGb(NF_BASE + 0x8)
 #define NFDATA		__REGb(NF_BASE + 0xc)
 #define NFSTAT		__REGb(NF_BASE + 0x10)
+#define NFSTAT_BUSY	1
+#define nand_select()	(NFCONF &= ~0x800)
+#define nand_deselect()	(NFCONF |= 0x800)
+#define nand_clear_RnB()	do {} while (0)
+#elif defined(CONFIG_S3C2440)
+#define NFCONF		__REGi(NF_BASE + 0x0)
+#define NFCONT		__REGi(NF_BASE + 0x4)
+#define NFCMD		__REGb(NF_BASE + 0x8)
+#define NFADDR		__REGb(NF_BASE + 0xc)
+#define NFDATA		__REGb(NF_BASE + 0x10)
+#define NFDATA16	__REGw(NF_BASE + 0x10)
+#define NFSTAT		__REGb(NF_BASE + 0x20)
+#define NFSTAT_BUSY	1
+#define nand_select()	(NFCONT &= ~(1 << 1))
+#define nand_deselect()	(NFCONT |= (1 << 1))
+#define nand_clear_RnB()	(NFSTAT |= (1 << 2))
+#endif
 
-#define BUSY 1
-inline void wait_idle(void)
+static inline void nand_wait(void)
 {
 	int i;
 
-	while (!(NFSTAT & BUSY))
+	while (!(NFSTAT & NFSTAT_BUSY))
 		for (i=0; i<10; i++);
 }
 
-#define NAND_SECTOR_SIZE	512
-#define NAND_BLOCK_MASK		(NAND_SECTOR_SIZE - 1)
-#define NAND_PAGE_SIZE		0x4000
+#if defined(CONFIG_S3C2410)
+/* configuration for 2410 with 512byte sized flash */
+#define NAND_PAGE_SIZE		512
+#define BAD_BLOCK_OFFSET	517
+#define NAND_BLOCK_MASK		(NAND_PAGE_SIZE - 1)
+#define NAND_BLOCK_SIZE		0x4000
+#else
+/* configuration for 2440 with 2048byte sized flash */
+#define NAND_5_ADDR_CYCLE
+#define NAND_PAGE_SIZE		2048
+#define BAD_BLOCK_OFFSET	NAND_PAGE_SIZE
+#define	NAND_BLOCK_MASK		(NAND_PAGE_SIZE - 1)
+#define NAND_BLOCK_SIZE		(NAND_PAGE_SIZE * 64)
+#endif
+
+/* compile time failure in case of an invalid configuration */
+#if defined(CONFIG_S3C2410) && (NAND_PAGE_SIZE != 512)
+#error "S3C2410 does not support nand page size != 512"
+#endif
+
+static int is_bad_block(unsigned long i)
+{