uboot-s3c2442.patch

Uboot常用的移植patches, 方便定制移植到s3c2440

Index: u-boot/cpu/arm920t/s3c24x0/cmd_s3c24xx.c
===================================================================
--- u-boot.orig/cpu/arm920t/s3c24x0/cmd_s3c24xx.c
+++ u-boot/cpu/arm920t/s3c24x0/cmd_s3c24xx.c
@@ -29,7 +29,7 @@
 #include <net.h>		/* for print_IPaddr */
 #if defined(CONFIG_S3C2410)
 #include <s3c2410.h>
-#elif defined(CONFIG_S3C2440)
+#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
 #include <s3c2440.h>
 #endif
 
@@ -58,7 +58,7 @@ struct s3c24x0_pll_speed {
 #define CLKDIVN_1_2_4	0x03
 #define CLKDIVN_1_4_4	0x04
 
-#if defined(CONFIG_S3C2440)
+#if defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
 #define CLKDIVN_1_4_8	0x05
 #define CLKDIVN_1_3_6	0x07
 #endif
@@ -142,6 +142,67 @@ static const struct s3c24x0_pll_speed pl
 #error "clock frequencies != 12MHz / 16.9344MHz not supported"
 #endif
 };
+#elif defined(CONFIG_S3C2442)
+#if (CONFIG_SYS_CLK_FREQ == 12000000)
+/* The value suggested in the user manual ((80 << 12) + (8 << 4) + 1) leads to
+ * 52MHz, i.e. completely wrong */
+static const u_int32_t upllcon = ((88 << 12) + (4 << 4) + 2);
+static const struct s3c24x0_pll_speed pll_configs[] = {
+	{
+		.mhz = 200,
+		.mpllcon = ((42 << 12) + (1 << 4) + 1),
+		.clkdivn = CLKDIVN_1_2_4,
+		.camdivn = 0,
+	},
+	{
+		.mhz = 300,
+		.mpllcon = ((67 << 12) + (1 << 4) + 1),
+		.clkdivn = CLKDIVN_1_3_6,
+		.camdivn = 0,
+	},
+	{
+		/* Make sure you are running at 1.4VDDiarm if you use this mode*/
+		.mhz = 400,
+		.mpllcon = ((42 << 12) + (1 << 4) + 0),
+		.clkdivn = CLKDIVN_1_4_8,
+		.camdivn = 0,
+	},
+	{
+		/* This is MSP54 specific, as per openmoko calculations */
+		/* Make sure you are running at 1.7VDDiarm if you use this mode*/
+		.mhz = 500,
+		.mpllcon = ((96 << 12) + (3 << 4) + 0),
+		.clkdivn = CLKDIVN_1_4_8,
+		.camdivn = 0,
+	},
+#elif (CONFIG_SYS_CLK_FREQ == 16934400)
+static const u_int32_t upllcon = ((26 << 12) + (4 << 4) + 1);
+static const struct s3c24x0_pll_speed pll_configs[] = {
+	{
+		.mhz = 296,
+		.mpllcon = ((62 << 12) + (1 << 4) + 2),
+		.clkdivn = CLKDIVN_1_3_6,
+		.camdivn = 0,
+	},
+	{
+		/* Make sure you are running at 1.4VDDiarm if you use this mode*/
+		.mhz = 400,
+		.mpllcon = ((63 << 12) + (4 << 4) + 0),
+		.clkdivn = CLKDIVN_1_4_8,
+		.camdivn = 0,
+	},
+	{
+		/* This is MSP54 specific, as per data sheet. */
+		/* Make sure you are running at 1.7VDDiarm if you use this mode*/
+		.mhz = 500,
+		.mpllcon = ((110 << 12) + (2 << 4) + 1),
+		.clkdivn = CLKDIVN_1_4_8,
+		.camdivn = 0,
+	},
+#else
+#error "clock frequencies != 12MHz / 16.9344MHz not supported"
+#endif
+};
 #else
 #error "please define valid pll configurations for your cpu type"
 #endif
Index: u-boot/cpu/arm920t/s3c24x0/i2c.c
===================================================================
--- u-boot.orig/cpu/arm920t/s3c24x0/i2c.c
+++ u-boot/cpu/arm920t/s3c24x0/i2c.c
@@ -34,7 +34,7 @@
 #include <s3c2400.h>
 #elif defined(CONFIG_S3C2410)
 #include <s3c2410.h>
-#elif defined(CONFIG_S3C2440)
+#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
 #include <s3c2440.h>
 #endif
 #include <i2c.h>
@@ -65,7 +65,8 @@ static int GetI2CSDA(void)
 {
 	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
 
-#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
+    defined(CONFIG_S3C2442)
 	return (gpio->GPEDAT & 0x8000) >> 15;
 #endif
 #ifdef CONFIG_S3C2400
@@ -84,7 +85,8 @@ static void SetI2CSCL(int x)
 {
 	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
 
-#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
+    defined(CONFIG_S3C2442)
 	gpio->GPEDAT = (gpio->GPEDAT & ~0x4000) | (x&1) << 14;
 #endif
 #ifdef CONFIG_S3C2400
@@ -141,7 +143,8 @@ void i2c_init (int speed, int slaveadd)
 	}
 
 	if ((status & I2CSTAT_BSY) || GetI2CSDA () == 0) {
-#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
+    defined(CONFIG_S3C2442)
 		ulong old_gpecon = gpio->GPECON;
 #endif
 #ifdef CONFIG_S3C2400
@@ -149,7 +152,8 @@ void i2c_init (int speed, int slaveadd)
 #endif
 		/* bus still busy probably by (most) previously interrupted transfer */
 
-#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
+    defined(CONFIG_S3C2442)
 		/* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
 		gpio->GPECON = (gpio->GPECON & ~0xF0000000) | 0x10000000;
 #endif
@@ -173,7 +177,8 @@ void i2c_init (int speed, int slaveadd)
 		udelay (1000);
 
 		/* restore pin functions */
-#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
+    defined(CONFIG_S3C2442)
 		gpio->GPECON = old_gpecon;
 #endif
 #ifdef CONFIG_S3C2400
Index: u-boot/cpu/arm920t/s3c24x0/interrupts.c
===================================================================
--- u-boot.orig/cpu/arm920t/s3c24x0/interrupts.c
+++ u-boot/cpu/arm920t/s3c24x0/interrupts.c
@@ -31,14 +31,15 @@
 
 #include <common.h>
 #if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || \
-    defined(CONFIG_S3C2440) || defined (CONFIG_TRAB)
+    defined(CONFIG_S3C2440) || defined (CONFIG_S3C2442) || \
+    defined (CONFIG_TRAB)
 
 #include <arm920t.h>
 #if defined(CONFIG_S3C2400)
 #include <s3c2400.h>
 #elif defined(CONFIG_S3C2410)
 #include <s3c2410.h>
-#elif defined(CONFIG_S3C2440)
+#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
 #include <s3c2440.h>
 #endif
 
@@ -62,7 +63,7 @@ int interrupt_init (void)
 	/* use PWM Timer 4 because it has no output */
 	/* prescaler for Timer 4 is 16 */
 	timers->TCFG0 = 0x0f00;
-#ifndef CONFIG_S3C2440
+#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
 	if (timer_load_val == 0)
 	{
 		/*
@@ -241,4 +242,5 @@ void s3c2410_irq(void)
 #endif /* USE_IRQ */
 
 #endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) ||
-	  defined(CONFIG_S3C2440) || defined (CONFIG_TRAB) */
+	  defined(CONFIG_S3C2440) || defined (CONFIG_S3C2442) ||
+	  defined (CONFIG_TRAB) */
Index: u-boot/cpu/arm920t/s3c24x0/mmc.c
===================================================================
--- u-boot.orig/cpu/arm920t/s3c24x0/mmc.c
+++ u-boot/cpu/arm920t/s3c24x0/mmc.c
@@ -137,7 +137,7 @@ static int mmc_block_read(uchar *dst, ul
 	dcon |= S3C2410_SDIDCON_RXAFTERCMD|S3C2410_SDIDCON_XFER_RXSTART;
 	if (wide)
 		dcon |= S3C2410_SDIDCON_WIDEBUS;
-#if defined(CONFIG_S3C2440)
+#if defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
 	dcon |= S3C2440_SDIDCON_DS_WORD | S3C2440_SDIDCON_DATSTART;
 #endif
 	sdi->SDIDCON = dcon;
@@ -403,7 +403,7 @@ int mmc_init(int verbose)
 	//sdi->SDIPRE = 0x3e;  /* SDCLK = PCLK/2 / (SDIPRE+1) = 396kHz */
 	sdi->SDIPRE = 0x02;  /* 2410: SDCLK = PCLK/2 / (SDIPRE+1) = 11MHz */
 	sdi->SDIDTIMER = 0xffff;
-#elif defined(CONFIG_S3C2440)
+#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
 	sdi->SDIPRE = 0x05;  /* 2410: SDCLK = PCLK / (SDIPRE+1) = 11MHz */
 	sdi->SDIDTIMER = 0x7fffff;
 #endif
Index: u-boot/cpu/arm920t/s3c24x0/nand.c
===================================================================
--- u-boot.orig/cpu/arm920t/s3c24x0/nand.c
+++ u-boot/cpu/arm920t/s3c24x0/nand.c
@@ -58,7 +58,7 @@
 #define S3C2410_NFCONF_TWRPH0(x)   ((x)<<4)
 #define S3C2410_NFCONF_TWRPH1(x)   ((x)<<0)
 
-#elif defined(CONFIG_S3C2440)
+#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
 
 #define oNFCMD		0x8
 #define oNFADDR		0xc
@@ -147,7 +147,7 @@ static void s3c2410_hwcontrol(struct mtd
 	case NAND_CTL_SETNCE:
 #if defined(CONFIG_S3C2410)
 		NFCONF &= ~NFCONF_nFCE;
-#elif defined(CONFIG_S3C2440)
+#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
 		NFCONT &= ~NFCONF_nFCE;
 #endif
 		DEBUGN("NFCONF=0x%08x\n", NFCONF);
@@ -155,7 +155,7 @@ static void s3c2410_hwcontrol(struct mtd
 	case NAND_CTL_CLRNCE:
 #if defined(CONFIG_S3C2410)
 		NFCONF |= NFCONF_nFCE;
-#elif defined(CONFIG_S3C2440)
+#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
 		NFCONT &= ~NFCONF_nFCE;
 #endif
 		DEBUGN("NFCONF=0x%08x\n", NFCONF);
@@ -235,7 +235,7 @@ int __board_nand_init(struct nand_chip *
 	cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
 
 	NFCONF = cfg;
-#elif defined(CONFIG_S3C2440)
+#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
 	twrph0 = 7; twrph1 = 7; tacls = 7;
 	NFCONF = (tacls<<12)|(twrph0<<8)|(twrph1<<4)|(0<<0);
 	NFCONT = (0<<13)|(0<<12)|(0<<10)|(0<<9)|(0<<8)|(1<<6)|(1<<5)|(1<<4)|(1<<1)|(1<<0);
@@ -272,7 +272,7 @@ int __board_nand_init(struct nand_chip *
 	nand->options = 0;
 #endif
 
-#if defined(CONFIG_S3C2440)
+#if defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
 /*
 	nand_select();
 	nand_clear_RnB();
Index: u-boot/cpu/arm920t/s3c24x0/nand_read.c
===================================================================
--- u-boot.orig/cpu/arm920t/s3c24x0/nand_read.c
+++ u-boot/cpu/arm920t/s3c24x0/nand_read.c
@@ -34,7 +34,7 @@
 #define nand_select()	(NFCONF &= ~0x800)
 #define nand_deselect()	(NFCONF |= 0x800)
 #define nand_clear_RnB()	do {} while (0)
-#elif defined(CONFIG_S3C2440)
+#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
 #define NFCONF		__REGi(NF_BASE + 0x0)
 #define NFCONT		__REGi(NF_BASE + 0x4)
 #define NFCMD		__REGb(NF_BASE + 0x8)
@@ -142,7 +142,7 @@ static int nand_read_page_ll(unsigned ch
 		*buf = (NFDATA & 0xff);
 		buf++;
 	}
-#elif defined(CONFIG_S3C2440)
+#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
 	for (i = 0; i < NAND_PAGE_SIZE/2; i++) {
 		*ptr16 = NFDATA16;
 		ptr16++;
Index: u-boot/cpu/arm920t/s3c24x0/serial.c
===================================================================
--- u-boot.orig/cpu/arm920t/s3c24x0/serial.c
+++ u-boot/cpu/arm920t/s3c24x0/serial.c
@@ -20,13 +20,14 @@
 
 #include <common.h>
 #if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || \
-    defined(CONFIG_S3C2440) || defined (CONFIG_TRAB)
+    defined(CONFIG_S3C2440) || defined (CONFIG_S3C2442) || \
+    defined (CONFIG_TRAB)
 
 #if defined(CONFIG_S3C2400) || defined(CONFIG_TRAB)
 #include <s3c2400.h>
 #elif defined(CONFIG_S3C2410)
 #include <s3c2410.h>
-#elif defined(CONFIG_S3C2440)
+#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
 #include <s3c2440.h>
 #endif
 
@@ -305,4 +306,5 @@ struct serial_device s3c24xx_serial2_dev
 #endif /* CONFIG_SERIAL_MULTI */
 
 #endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) ||
-	  defined(CONFIG_S3C2440) || defined (CONFIG_TRAB) */
+	  defined(CONFIG_S3C2440) || defined (CONFIG_S3C2442) ||
+	  defined (CONFIG_TRAB) */
Index: u-boot/cpu/arm920t/s3c24x0/speed.c
===================================================================
--- u-boot.orig/cpu/arm920t/s3c24x0/speed.c
+++ u-boot/cpu/arm920t/s3c24x0/speed.c
@@ -31,13 +31,13 @@
 
 #include <common.h>
 #if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || \
-    defined (CONFIG_S3C2440) || defined (CONFIG_TRAB)
+    defined (CONFIG_S3C2440) || defined(CONFIG_S3C2442) || defined (CONFIG_TRAB)
 
 #if defined(CONFIG_S3C2400)
 #include <s3c2400.h>
 #elif defined(CONFIG_S3C2410)
 #include <s3c2410.h>
-#elif defined(CONFIG_S3C2440)
+#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
 #include <s3c2440.h>
 #endif
 
@@ -71,7 +71,7 @@ static ulong get_PLLCLK(int pllreg)
     s = r & 0x3;
 #if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
     return((CONFIG_SYS_CLK_FREQ * m) / (p << s));
-#elif defined(CONFIG_S3C2440)
+#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
     /* To avoid integer overflow, changed the calc order */
     if (pllreg == MPLL)
     	return ( 2 * m * (CONFIG_SYS_CLK_FREQ / (p << s )) );
@@ -95,7 +95,7 @@ ulong get_HCLK(void)
 
 #if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
     return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK());
-#elif defined(CONFIG_S3C2440)
+#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
     switch (clk_power->CLKDIVN & 0x6) {
         case 0x0:
 	    return get_FCLK();
@@ -127,4 +127,5 @@ ulong get_UCLK(void)
 }
 
 #endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) ||
-          defined(CONFIG_S3C2440) || defined (CONFIG_TRAB) */