📄 gta02-splash.patch
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+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,+ 0x8023, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, }; -#if 0-static struct glamo_script gl3362_init_script[] = {- /* clock */- { GLAMO_REG_CLOCK_MEMORY, 0x300a },+static u16 u16a_gen_init_0x0000[] = {+ 0x2020, 0x3650, 0x0002, 0x01FF, 0x0000, 0x0000, 0x0000, 0x0000,+ 0x000D, 0x000B, 0x00EE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,+ 0x1839, 0x0000, 0x2000, 0x0101, 0x0100, 0x0000, 0x0000, 0x0000,+ 0x05DB, 0x5231, 0x09C3, 0x8261, 0x0003, 0x0000, 0x0000, 0x0000,+ 0x000F, 0x101E, 0xC0C3, 0x101E, 0x000F, 0x0001, 0x030F, 0x020F,+ 0x080F, 0x0F0F };-#endif -static void glamo_run_script(struct glamo_script *script, int num)+static u16 u16a_gen_init_0x0200[] = {+ 0x0EF0, 0x07FF, 0x0000, 0x0080, 0x0344, 0x0600, 0x0000, 0x0000,+ 0x0000, 0x0000, 0x4000, 0xF00E, 0x00C0, 0x00C0, 0x00C0, 0x00C0,+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,+ 0x0873, 0xAFAF, 0x0108, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,+ 0x0000, 0x1002, 0x6006, 0x00FF, 0x0001, 0x0020, 0x0000, 0x0000,+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,+ 0x3210, 0x5432, 0xE100, 0x01D6+};++#define glamofb_cmdq_empty() (glamo_reg_read(GLAMO_REGOFS_LCD + \+ GLAMO_REG_LCD_STATUS1) & (1 << 15))++void glamofb_cmd_mode(int on) {- int i;- for (i = 0; i < ARRAY_SIZE(gl3362_init_script); i++) {- struct glamo_script *reg = script + i;- printf("reg=0x%04x, val=0x%04x\n", reg->reg, reg->val);-- if (reg->reg == 0xfffe)- udelay(reg->val*1000);- else- glamo_reg_write(reg->reg, reg->val);+ if (on) {+ while (!glamofb_cmdq_empty())+ ;+ /* display the entire frame then switch to command */+ glamo_reg_write(GLAMO_REGOFS_LCD + GLAMO_REG_LCD_COMMAND1,+ GLAMO_LCD_CMD_TYPE_DISP |+ GLAMO_LCD_CMD_DATA_FIRE_VSYNC);++ while (!(glamo_reg_read(GLAMO_REGOFS_LCD ++ GLAMO_REG_LCD_STATUS2) & (1 << 12)))+ ;+ udelay(5000); /* you really need this ;-) */+ } else {+ /* RGB interface needs vsync/hsync */+ if (glamo_reg_read(GLAMO_REGOFS_LCD + GLAMO_REG_LCD_MODE3) &+ GLAMO_LCD_MODE3_RGB)+ glamo_reg_write(GLAMO_REGOFS_LCD ++ GLAMO_REG_LCD_COMMAND1,+ GLAMO_LCD_CMD_TYPE_DISP |+ GLAMO_LCD_CMD_DATA_DISP_SYNC);++ glamo_reg_write(GLAMO_REGOFS_LCD + GLAMO_REG_LCD_COMMAND1,+ GLAMO_LCD_CMD_TYPE_DISP |+ GLAMO_LCD_CMD_DATA_DISP_FIRE); }+} +void glamofb_cmd_write(u_int16_t val)+{+ while (!glamofb_cmdq_empty())+ ;+ glamo_reg_write(GLAMO_REGOFS_LCD + GLAMO_REG_LCD_COMMAND1, val); } static void glamo_core_init(void) {- printf("Glamo core device ID: 0x%04x, Revision 0x%04x\n",- glamo_reg_read(GLAMO_REG_DEVICE_ID),- glamo_reg_read(GLAMO_REG_REVISION_ID));+ int bp; - glamo_run_script(gl3362_init_script, ARRAY_SIZE(gl3362_init_script));+ /* power up PLL1 and PLL2 */+ glamo_reg_write(GLAMO_REG_PLL_GEN7, 0x0000);+ glamo_reg_write(GLAMO_REG_PLL_GEN3, 0x0400);++ /* enable memory clock and get it out of deep pwrdown */+ glamo_reg_write(GLAMO_REG_CLOCK_MEMORY,+ glamo_reg_read(GLAMO_REG_CLOCK_MEMORY) |+ GLAMO_CLOCK_MEM_EN_MOCACLK);+ glamo_reg_write(GLAMO_REG_MEM_DRAM2,+ glamo_reg_read(GLAMO_REG_MEM_DRAM2) &+ (~GLAMO_MEM_DRAM2_DEEP_PWRDOWN));+ glamo_reg_write(GLAMO_REG_MEM_DRAM1,+ glamo_reg_read(GLAMO_REG_MEM_DRAM1) &+ (~GLAMO_MEM_DRAM1_SELF_REFRESH));+ /*+ * we just fill up the general hostbus and LCD register sets+ * with magic values taken from the Linux framebuffer init action+ */+ for (bp = 0; bp < ARRAY_SIZE(u16a_gen_init_0x0000); bp++)+ glamo_reg_write(GLAMO_REGOFS_GENERIC | (bp << 1),+ u16a_gen_init_0x0000[bp]);++ for (bp = 0; bp < ARRAY_SIZE(u16a_gen_init_0x0200); bp++)+ glamo_reg_write(GLAMO_REGOFS_HOSTBUS | (bp << 1),+ u16a_gen_init_0x0200[bp]);+ + /* spin until PLL1 lock */+ while (!(glamo_reg_read(GLAMO_REG_PLL_GEN5) & 1))+ ;++ glamofb_cmd_mode(1);+ /* LCD registers */+ for (bp = 0; bp < ARRAY_SIZE(u16a_lcd_init); bp++)+ glamo_reg_write(GLAMO_REGOFS_LCD + (bp << 1),+ u16a_lcd_init[bp]);+ glamofb_cmd_mode(0); } -void *video_hw_init(void)+void * video_hw_init(void) {- u_int16_t reg; GraphicDevice *pGD = (GraphicDevice *)&smi; - glamo_core_init();-- printf("Video: ");+ printf("Glamo core device ID: 0x%04x, Revision 0x%04x\n",+ glamo_reg_read(GLAMO_REG_DEVICE_ID),+ glamo_reg_read(GLAMO_REG_REVISION_ID)); - /* FIXME: returning since vram access still locks up system */- return NULL;+ glamo_core_init(); - /* FIXME: this is static */ pGD->winSizeX = pGD->plnSizeX = 480; pGD->winSizeY = pGD->plnSizeY = 640; pGD->gdfBytesPP = 2;@@ -170,16 +223,21 @@ void *video_hw_init(void) pGD->frameAdrs = CONFIG_GLAMO_BASE + 0x00800000; pGD->memSize = 0x200000; /* 480x640x16bit = 614400 bytes */ - //printf("memset ");- //memset(pGD->frameAdrs, 0, pGD->memSize);-- printf("END\n");+#ifdef CONFIG_GTA02_REVISION+ /* bring up the LCM */+ smedia3362_lcm_reset(1);+ if (getenv("splashimage"))+ run_command(getenv("splashimage"), 0);+ jbt6k74_enter_state(JBT_STATE_NORMAL);+ jbt6k74_display_onoff(1);+ /* switch on the backlight */+ neo1973_backlight(1);+#endif return &smi; } -void-video_set_lut(unsigned int index, unsigned char r,+void video_set_lut(unsigned int index, unsigned char r, unsigned char g, unsigned char b) { /* FIXME: we don't support any palletized formats */Index: u-boot/drivers/video/smedia3362.h===================================================================--- u-boot.orig/drivers/video/smedia3362.h+++ u-boot/drivers/video/smedia3362.h@@ -101,6 +101,42 @@ enum glamo_register_generic { GLAMO_REG_PLL_GEN7 = 0x01f0, }; +enum glamo_reg_mem_dram1 {+ GLAMO_MEM_DRAM1_EN_SDRAM_CLK = (1 << 11),+ GLAMO_MEM_DRAM1_SELF_REFRESH = (1 << 12),+};++enum glamo_reg_mem_dram2 {+ GLAMO_MEM_DRAM2_DEEP_PWRDOWN = (1 << 12),+};++enum glamo_reg_clock51 {+ GLAMO_CLOCK_GEN51_EN_DIV_MCLK = 0x0001,+ GLAMO_CLOCK_GEN51_EN_DIV_SCLK = 0x0002,+ GLAMO_CLOCK_GEN51_EN_DIV_JCLK = 0x0004,+ GLAMO_CLOCK_GEN51_EN_DIV_DCLK = 0x0008,+ GLAMO_CLOCK_GEN51_EN_DIV_DMCLK = 0x0010,+ GLAMO_CLOCK_GEN51_EN_DIV_DHCLK = 0x0020,+ GLAMO_CLOCK_GEN51_EN_DIV_GCLK = 0x0040,+ GLAMO_CLOCK_GEN51_EN_DIV_TCLK = 0x0080,+ /* FIXME: higher bits */+};++enum glamo_reg_hostbus2 {+ GLAMO_HOSTBUS2_MMIO_EN_ISP = 0x0001,+ GLAMO_HOSTBUS2_MMIO_EN_JPEG = 0x0002,+ GLAMO_HOSTBUS2_MMIO_EN_MPEG = 0x0004,+ GLAMO_HOSTBUS2_MMIO_EN_LCD = 0x0008,+ GLAMO_HOSTBUS2_MMIO_EN_MMC = 0x0010,+ GLAMO_HOSTBUS2_MMIO_EN_MICROP0 = 0x0020,+ GLAMO_HOSTBUS2_MMIO_EN_MICROP1 = 0x0040,+ GLAMO_HOSTBUS2_MMIO_EN_CQ = 0x0080,+ GLAMO_HOSTBUS2_MMIO_EN_RISC = 0x0100,+ GLAMO_HOSTBUS2_MMIO_EN_2D = 0x0200,+ GLAMO_HOSTBUS2_MMIO_EN_3D = 0x0400,+};++ #define GLAMO_REG_HOSTBUS(x) (GLAMO_REGOFS_HOSTBUS-2+(x*2)) #define REG_MEM(x) (GLAMO_REGOFS_MEMORY+(x))@@ -330,6 +366,7 @@ enum glamo_reg_lcd { GLAMO_REG_LCD_SRAM_DRIVING3 = REG_LCD(0x164), }; + enum glamo_reg_lcd_mode1 { GLAMO_LCD_MODE1_PWRSAVE = 0x0001, GLAMO_LCD_MODE1_PARTIAL_PRT = 0x0002,@@ -382,4 +419,41 @@ enum glamo_reg_lcd_mode3 { GLAMO_LCD_MODE3_18BITS = 0x0040, }; +enum glamo_lcd_cmd_type {+ GLAMO_LCD_CMD_TYPE_DISP = 0x0000,+ GLAMO_LCD_CMD_TYPE_PARALLEL = 0x4000,+ GLAMO_LCD_CMD_TYPE_SERIAL = 0x8000,+ GLAMO_LCD_CMD_TYPE_SERIAL_DIRECT= 0xc000,+};+#define GLAMO_LCD_CMD_TYPE_MASK 0xc000++enum glamo_lcd_cmds {+ GLAMO_LCD_CMD_DATA_DISP_FIRE = 0x00,+ GLAMO_LCD_CMD_DATA_DISP_SYNC = 0x01, /* RGB only */+ /* switch to command mode, no display */+ GLAMO_LCD_CMD_DATA_FIRE_NO_DISP = 0x02,+ /* display until VSYNC, switch to command */+ GLAMO_LCD_CMD_DATA_FIRE_VSYNC = 0x11,+ /* display until HSYNC, switch to command */+ GLAMO_LCD_CMD_DATA_FIRE_HSYNC = 0x12,+ /* display until VSYNC, 1 black frame, VSYNC, switch to command */+ GLAMO_LCD_CMD_DATA_FIRE_VSYNC_B = 0x13,+ /* don't care about display and switch to command */+ GLAMO_LCD_CMD_DATA_FIRE_FREE = 0x14, /* RGB only */+ /* don't care about display, keep data display but disable data,+ * and switch to command */+ GLAMO_LCD_CMD_DATA_FIRE_FREE_D = 0x15, /* RGB only */+};++enum glamo_reg_clock_2d {+ GLAMO_CLOCK_2D_DG_GCLK = 0x0001,+ GLAMO_CLOCK_2D_EN_GCLK = 0x0002,+ GLAMO_CLOCK_2D_DG_M7CLK = 0x0004,+ GLAMO_CLOCK_2D_EN_M7CLK = 0x0008,+ GLAMO_CLOCK_2D_DG_M6CLK = 0x0010,+ GLAMO_CLOCK_2D_EN_M6CLK = 0x0020,+ GLAMO_CLOCK_2D_RESET = 0x1000,+ GLAMO_CLOCK_2D_CQ_RESET = 0x2000,+};+ #endif /* _GLAMO_REGS_H */Index: u-boot/include/configs/neo1973_gta02.h===================================================================--- u-boot.orig/include/configs/neo1973_gta02.h+++ u-boot/include/configs/neo1973_gta02.h@@ -251,12 +251,12 @@ /* we have a board_late_init() function */ #define BOARD_LATE_INIT 1 -#if 0+#if 1 #define CONFIG_VIDEO #define CONFIG_VIDEO_GLAMO3362 #define CONFIG_CFB_CONSOLE-#define CONFIG_VIDEO_LOGO-#define CONFIG_SPLASH_SCREEN+//#define CONFIG_VIDEO_LOGO+//#define CONFIG_SPLASH_SCREEN #define CFG_VIDEO_LOGO_MAX_SIZE (640*480+1024+100) /* 100 = slack */ #define CONFIG_VIDEO_BMP_GZIP #define CONFIG_VGA_AS_SINGLE_DEVICE⌨️ 快捷键说明
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