📄 uboot-smdk2443.patch
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+#define CFG_ATA_BASE_ADDR+#endif++#define CONFIG_USB_OHCI_NEW 1+#define CFG_USB_OHCI_CPU_INIT 1+#define CFG_USB_OHCI_REGS_BASE 0x49000000 /* S3C24X0_USB_HOST_BASE */+#define CFG_USB_OHCI_SLOT_NAME "s3c2443"+#define CFG_USB_OHCI_MAX_ROOT_PORTS 2++#define CONFIG_USB_DEVICE 1+#define CONFIG_USB_TTY 1+#define CFG_CONSOLE_IS_IN_ENV 1+#define CONFIG_USBD_VENDORID 0x1457 /* Linux/NetChip */+#define CONFIG_USBD_PRODUCTID_GSERIAL 0x5120 /* gserial */+#define CONFIG_USBD_PRODUCTID_CDCACM 0x5119 /* CDC ACM */+#define CONFIG_USBD_MANUFACTURER "FiWin"+#define CONFIG_USBD_PRODUCT_NAME "S3C2443 Bootloader " U_BOOT_VERSION+#define CONFIG_EXTRA_ENV_SETTINGS "usbtty=cdc_acm\0"+#define CONFIG_USBD_DFU 1+#define CONFIG_USBD_DFU_XFER_SIZE 4096+#define CONFIG_USBD_DFU_INTERFACE 2++/*-----------------------------------------------------------------------+ * Physical Memory Map+ */+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */+#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */++#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */++#define CFG_FLASH_BASE PHYS_FLASH_1++/*-----------------------------------------------------------------------+ * FLASH and environment organization+ */++#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */+#if 0+#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */+#endif++#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */+#ifdef CONFIG_AMD_LV800+#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */+#define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */+#endif+#ifdef CONFIG_AMD_LV400+#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */+#define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */+#endif++/* timeout values are in ticks */+#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */+#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */++#define CFG_ENV_IS_IN_NAND 1+#define CFG_ENV_SIZE 0x20000 /* 128k Total Size of Environment Sector */+#define CFG_ENV_OFFSET_OOB 1+#define CFG_PREBOOT_OVERRIDE 1++#define NAND_MAX_CHIPS 1+#define CFG_NAND_BASE 0x4e000000+#define CFG_MAX_NAND_DEVICE 1++#define CONFIG_MMC 1+#define CFG_MMC_BASE 0xff000000++#define CONFIG_EXT2 1++/* FAT driver in u-boot is broken currently */+#define CONFIG_FAT 1+#define CONFIG_SUPPORT_VFAT++#if 1+/* JFFS2 driver */+#define CONFIG_JFFS2_CMDLINE 1+#define CONFIG_JFFS2_NAND 1+#define CONFIG_JFFS2_NAND_DEV 0+//#define CONFIG_JFFS2_NAND_OFF 0x634000+//#define CONFIG_JFFS2_NAND_SIZE 0x39cc000+#endif++/* ATAG configuration */+#define CONFIG_INITRD_TAG 1+#define CONFIG_SETUP_MEMORY_TAGS 1+#define CONFIG_CMDLINE_TAG 1+#if 0+#define CONFIG_SERIAL_TAG 1+#define CONFIG_REVISION_TAG 1+#endif+++#if 0+#define CONFIG_VIDEO+#define CONFIG_VIDEO_S3C2410+#define CONFIG_CFB_CONSOLE+#define CONFIG_VIDEO_LOGO+#define CONFIG_VGA_AS_SINGLE_DEVICE++#define VIDEO_KBD_INIT_FCT 0+#define VIDEO_TSTC_FCT serial_tstc+#define VIDEO_GETC_FCT serial_getc++#define LCD_VIDEO_ADDR 0x33d00000+#endif++#define CONFIG_S3C2410_NAND_BBT 1+//#define CONFIG_S3C2410_NAND_HWECC 1++#define CFG_NAND_YAFFS_WRITE+#define CFG_NAND_YAFFS1_NEW_OOB_LAYOUT++#define MTDIDS_DEFAULT "nand0=smdk2443-nand"+#define MTPARTS_DEFAULT "smdk2443-nand:0x00100000(u-boot),0x00200000(kernel),0x00200000(update),0x00100000(splash),0x01400000(jffs2),-(temp)"+#define CFG_NAND_DYNPART_MTD_KERNEL_NAME "smdk2443-nand"+#define CONFIG_NAND_DYNPART++#endif /* __CONFIG_H */Index: u-boot/board/smdk2443/lowlevel_foo.S===================================================================--- /dev/null+++ u-boot/board/smdk2443/lowlevel_foo.S@@ -0,0 +1,82 @@++_start:+ b reset+undefvec:+ b undefvec+swivec:+ b swivec+pabtvec:+ b pabtvec+dabtvec:+ b dabtvec+rsvdvec:+ b rsvdvec+irqvec:+ b irqvec+fiqvec:+ b fiqvec++reset:+ /*+ * set the cpu to SVC32 mode+ */+ mrs r0,cpsr+ bic r0,r0,#0x1f+ orr r0,r0,#0xd3+ msr cpsr,r0++/* turn off the watchdog */+#define pWTCON 0x53000000+#define INTMSK 0x4A000008 /* Interupt-Controller base addresses */+#define INTSUBMSK 0x4A00001C+#define CLKDIVN 0x4C000014 /* clock divisor register */++ ldr r0, =pWTCON+ mov r1, #0x0+ str r1, [r0]++ mov r1, #0xffffffff+ ldr r0, =INTMSK+ str r1, [r0]+ ldr r1, =0x3ff+ ldr r0, =INTSUBMSK+ str r1, [r0]++ /* FCLK:HCLK:PCLK = 1:2:4 */+ /* default FCLK is 120 MHz ! */+ ldr r0, =CLKDIVN+ mov r1, #3+ str r1, [r0]++ bl cpu_init_crit+ ldr r0,=TEXT_BASE+ mov pc, r0++cpu_init_crit:+ /*+ * flush v4 I/D caches+ */+ mov r0, #0+ mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */+ mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */++ /*+ * disable MMU stuff and caches+ */+ mrc p15, 0, r0, c1, c0, 0+ bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)+ bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)+ orr r0, r0, #0x00000002 @ set bit 2 (A) Align+ orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache+ mcr p15, 0, r0, c1, c0, 0++ /*+ * before relocating, we have to setup RAM timing+ * because memory timing is board-dependend, you will+ * find a lowlevel_init.S in your board directory.+ */+ mov ip, lr+ bl lowlevel_init+ mov lr, ip+ mov pc, lr+Index: u-boot/board/smdk2443/lowlevel_init.S===================================================================--- /dev/null+++ u-boot/board/smdk2443/lowlevel_init.S@@ -0,0 +1,163 @@+/*+ * SMDK2443 Memory Setup+ *+ * Copyright (C) 2007 by OpenMoko, Inc.+ * Author: Harald Welte <laforge@openmoko.org>+ *+ * See file CREDITS for list of people who contributed to this+ * project.+ *+ * This program is free software; you can redistribute it and/or+ * modify it under the terms of the GNU General Public License as+ * published by the Free Software Foundation; either version 2 of+ * the License, or (at your option) any later version.+ *+ * This program is distributed in the hope that it will be useful,+ * but WITHOUT ANY WARRANTY; without even the implied warranty of+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the+ * GNU General Public License for more details.+ *+ * You should have received a copy of the GNU General Public License+ * along with this program; if not, write to the Free Software+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,+ * MA 02111-1307 USA+ */+++#include <config.h>+#include <version.h>+++/* some parameters for the board */++/*+ *+ * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S+ *+ * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com>+ *+ */++#define BWSCON 0x48000000++/* BWSCON */+#define DW8 (0x0)+#define DW16 (0x1)+#define DW32 (0x2)+#define WAIT (0x1<<2)+#define UBLB (0x1<<3)++#define B1_BWSCON (DW32)+#define B2_BWSCON (DW16)+#define B3_BWSCON (DW16 + WAIT + UBLB)+#define B4_BWSCON (DW16)+#define B5_BWSCON (DW16)+#define B6_BWSCON (DW32)+#define B7_BWSCON (DW32)++/* BANK0CON */+#define B0_Tacs 0x0 /* 0clk */+#define B0_Tcos 0x0 /* 0clk */+#define B0_Tacc 0x7 /* 14clk */+#define B0_Tcoh 0x0 /* 0clk */+#define B0_Tah 0x0 /* 0clk */+#define B0_Tacp 0x0+#define B0_PMC 0x0 /* normal */++/* BANK1CON */+#define B1_Tacs 0x0 /* 0clk */+#define B1_Tcos 0x0 /* 0clk */+#define B1_Tacc 0x7 /* 14clk */+#define B1_Tcoh 0x0 /* 0clk */+#define B1_Tah 0x0 /* 0clk */+#define B1_Tacp 0x0+#define B1_PMC 0x0++#define B2_Tacs 0x0+#define B2_Tcos 0x0+#define B2_Tacc 0x7+#define B2_Tcoh 0x0+#define B2_Tah 0x0+#define B2_Tacp 0x0+#define B2_PMC 0x0++#define B3_Tacs 0x0 /* 0clk */+#define B3_Tcos 0x3 /* 4clk */+#define B3_Tacc 0x7 /* 14clk */+#define B3_Tcoh 0x1 /* 1clk */+#define B3_Tah 0x0 /* 0clk */+#define B3_Tacp 0x3 /* 6clk */+#define B3_PMC 0x0 /* normal */++#define B4_Tacs 0x0 /* 0clk */+#define B4_Tcos 0x0 /* 0clk */+#define B4_Tacc 0x7 /* 14clk */+#define B4_Tcoh 0x0 /* 0clk */+#define B4_Tah 0x0 /* 0clk */+#define B4_Tacp 0x0+#define B4_PMC 0x0 /* normal */++#define B5_Tacs 0x0 /* 0clk */+#define B5_Tcos 0x0 /* 0clk */+#define B5_Tacc 0x7 /* 14clk */+#define B5_Tcoh 0x0 /* 0clk */+#define B5_Tah 0x0 /* 0clk */+#define B5_Tacp 0x0+#define B5_PMC 0x0 /* normal */++#define B6_MT 0x3 /* SDRAM */+#define B6_Trcd 0x1+#define B6_SCAN 0x1 /* 9bit */++#define B7_MT 0x3 /* SDRAM */+#define B7_Trcd 0x1 /* 3clk */+#define B7_SCAN 0x1 /* 9bit */++/* REFRESH parameter */+#define REFEN 0x1 /* Refresh enable */+#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */+#define Trp 0x0 /* 2clk */+#define Trc 0x3 /* 7clk */+#define Tchr 0x2 /* 3clk */+#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */+/**************************************/++_TEXT_BASE:+ .word TEXT_BASE++.globl lowlevel_init+lowlevel_init:+ /* memory control configuration */+ /* make r0 relative the current location so that it */+ /* reads SMRDATA out of FLASH rather than memory ! */+ ldr r0, =SMRDATA+ ldr r1, _TEXT_BASE+ sub r0, r0, r1+ ldr r1, =BWSCON /* Bus Width Status Controller */+ add r2, r0, #13*4+0:+ ldr r3, [r0], #4+ str r3, [r1], #4+ cmp r2, r0+ bne 0b++ /* everything is fine now */+ mov pc, lr++ .ltorg+/* the literal pools origin */++SMRDATA:+ .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))+ .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))+ .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))+ .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))+ .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))+ .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))+ .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))+ .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))+ .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))+ .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)+ .word 0x32+ .word 0x30+ .word 0x30Index: u-boot/board/smdk2443/config.mk===================================================================--- /dev/null+++ u-boot/board/smdk2443/config.mk@@ -0,0 +1,29 @@+#+# (C) Copyright 2002+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>+#+# SAMSUNG SMDK2443 board with S3C2443 (ARM920T) cpu+#+# see http://www.samsung.com/ for more information on SAMSUNG+#++CONFIG_USB_DFU_VENDOR=0x1457+CONFIG_USB_DFU_PRODUCT=0x511c+CONFIG_USB_DFU_REVISION=0x0100++#+# SMDK2443 has 1 bank of 64 MB DRAM+#+# 3000'0000 to 3400'0000+#+# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000+# optionally with a ramdisk at 3080'0000+#+# we load ourself to 33F8'0000+#+# download area is 3300'0000+#+++TEXT_BASE = 0x33F80000Index: u-boot/board/smdk2443/lowlevel_foo.lds===================================================================--- /dev/null+++ u-boot/board/smdk2443/lowlevel_foo.lds@@ -0,0 +1,56 @@+/*+ * (C) Copyright 2002+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>+ *+ * See file CREDITS for list of people who contributed to this+ * project.+ *+ * This program is free software; you can redistribute it and/or+ * modify it under the terms of the GNU General Public License as+ * published by the Free Software Foundation; either version 2 of+ * the License, or (at your option) any later version.+ *+ * This program is distributed in the hope that it will be useful,+ * but WITHOUT ANY WARRANTY; without even the implied warranty of+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the+ * GNU General Public License for more details.+ *+ * You should have received a copy of the GNU General Public License+ * along with this program; if not, write to the Free Software+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,+ * MA 02111-1307 USA+ */++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")+OUTPUT_ARCH(arm)+ENTRY(_start)+SECTIONS+{+ . = 0x00000000;++ . = ALIGN(4);+ .text :+ {+ lowlevel_foo.o (.text)+ *(.text)+ }++ . = ALIGN(4);+ .rodata : { *(.rodata) }++ . = ALIGN(4);+ .data : { *(.data) }++ . = ALIGN(4);+ .got : { *(.got) }++ . = .;+ __u_boot_cmd_start = .;+ .u_boot_cmd : { *(.u_boot_cmd) }+ __u_boot_cmd_end = .;++ . = ALIGN(4);+ __bss_start = .;+ .bss : { *(.bss) }+ _end = .;+}Index: u-boot/board/smdk2443/flash.c===================================================================--- /dev/null+++ u-boot/board/smdk2443/flash.c⌨️ 快捷键说明
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