uboot-gta02.patch

Uboot常用的移植patches, 方便定制移植到s3c2440

+	[PCF50633_REG_DOWN1MXC]	= 0x22,	/* limit to 510mA at startup */
+
+	[PCF50633_REG_DOWN2OUT]	= 0x2f, /* 1.8V (0x2f * .025V + 0.625V) */
+#ifdef CONFIG_ARCH_GTA02_v1
+	[PCF50633_REG_DOWN2ENA]	= 0x02, /* enabled if GPIO1 = HIGH */
+#else
+	[PCF50633_REG_DOWN2ENA]	= 0x01, /* always enabled */
+#endif
+	[PCF50633_REG_DOWN2CTL]	= 0x00,	/* no DVM */
+	[PCF50633_REG_DOWN2MXC]	= 0x22, /* limit to 510mA at startup */
+
+	[PCF50633_REG_MEMLDOOUT] = 0x00,
+	[PCF50633_REG_MEMLDOENA] = 0x00,
+
+	[PCF50633_REG_LEDOUT]	= 0x2f,	/* full backlight power */
+	[PCF50633_REG_LEDENA]	= 0x02,	/* enabled if GPIO1 = HIGH */
+	[PCF50633_REG_LEDCTL]	= 0x05, /* ovp enabled, ocp 500mA */
+	[PCF50633_REG_LEDDIM]	= 0x20,	/* dimming curve */
+
+	[PCF50633_REG_LDO1OUT]	= 0x18,	/* 3.3V (24 * 0.1V + 0.9V) */
+#ifdef CONFIG_ARCH_GTA02_v1
+	[PCF50633_REG_LDO1ENA]	= 0x01,	/* always on */
+#else
+	[PCF50633_REG_LDO1ENA]	= 0x02, /* enabled if GPIO1 = HIGH */
+#endif
+
+	[PCF50633_REG_LDO2OUT]	= 0x18,	/* 3.3V (24 * 0.1V + 0.9V) */
+	[PCF50633_REG_LDO2ENA]	= 0x02, /* enabled if GPIO1 = HIGH */
+
+#ifdef CONFIG_ARCH_GTA02_v1
+	[PCF50633_REG_LDO3OUT]	= 0x15,	/* 3.0V (21 * 0.1V + 0.9V) */
+	[PCF50633_REG_LDO3ENA]	= 0x02, /* enabled if GPIO1 = HIGH */
+#else
+	[PCF50633_REG_LDO3OUT]	= 0x00,
+	[PCF50633_REG_LDO3ENA]	= 0x00,
+#endif
+
+	[PCF50633_REG_LDO4ENA]	= 0x00,
+
+#ifdef CONFIG_ARCH_GTA02_v1
+	[PCF50633_REG_LDO5ENA]	= 0x00,
+#else
+	[PCF50633_REG_LDO5OUT]	= 0x15, /* 3.0V (21 * 0.1V + 0.9V) */
+	[PCF50633_REG_LDO5ENA]	= 0x01, /* always on */
+#endif
+
+#ifdef CONFIG_ARCH_GTA02_v1
+	[PCF50633_REG_LDO6ENA]	= 0x00,
+#else
+	[PCF50633_REG_LDO6OUT]	= 0x15,	/* 3.0V (21 * 0.1V + 0.9V) */
+	[PCF50633_REG_LDO6ENA]	= 0x01,	/* always on */
+#endif
+
+	[PCF50633_REG_HCLDOOUT]	= 0x18,	/* 3.3V (24 * 0.1V + 0.9V) */
+	[PCF50633_REG_HCLDOENA]	= 0x00, /* off by default*/
+
+	[PCF50633_REG_DCDCPFM]	= 0x00, /* off by default*/
+
+	[PCF50633_REG_MBCC1]	= 0xe6,
+	[PCF50633_REG_MBCC2]	= 0x28,	/* Vbatconid=2.7V, Vmax=4.20V */
+	[PCF50633_REG_MBCC3]	= 0x19,	/* 25/255 == 98mA pre-charge */
+	[PCF50633_REG_MBCC4]	= 0xff, /* 255/255 == 1A adapter fast */
+	[PCF50633_REG_MBCC5]	= 0xff,	/* 255/255 == 1A usb fast */
+	[PCF50633_REG_MBCC6]	= 0x00, /* cutoff current 1/32 * Ichg */
+	[PCF50633_REG_MBCC7]	= 0x01,	/* 1.6A max bat curr, USB 500mA */
+	[PCF50633_REG_MBCC8]	= 0x00,
+
+	[PCF50633_REG_BBCCTL]	= 0x19,	/* 3V, 200uA, on */
+};
Index: u-boot/board/neo1973/gta02/config.mk
===================================================================
--- /dev/null
+++ u-boot/board/neo1973/gta02/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <[e-mail]>
+# David Mueller, ELSOFT AG, <[e-mail]>
+#
+# FIC Neo1973 GTA01 board with S3C2410X (ARM920T) cpu
+#
+# see http://www.samsung.com/ for more information on SAMSUNG
+#
+
+# GTA01v3 has 1 bank of 64 MB SDRAM
+# GTA01v4 has 1 bank of 64 MB SDRAM
+#
+# 	3000'0000 to 3400'0000
+# we load ourself to 33F8'0000
+#
+# GTA01Bv2 or later has 1 bank of 128 MB SDRAM
+#
+# 	3000'0000 to 3800'0000
+# we load ourself to 37F8'0000
+#
+# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
+# optionally with a ramdisk at 3080'0000
+#
+# download area is 3200'0000 or 3300'0000
+
+CONFIG_USB_DFU_VENDOR=0x1457
+CONFIG_USB_DFU_PRODUCT=0x5119
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+TEXT_BASE = 0x33F80000
Index: u-boot/drivers/video/smedia3362.c
===================================================================
--- /dev/null
+++ u-boot/drivers/video/smedia3362.c
@@ -0,0 +1,188 @@
+/*
+ * (C) Copyright 2007 by OpenMoko, Inc.
+ * Author: Harald Welte <[e-mail]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_VIDEO_GLAMO3362)
+
+#include <video_fb.h>
+#include "videomodes.h"
+#include <s3c2410.h>
+#include "smedia3362.h"
+
+#define ARRAY_SIZE(x)           (sizeof(x) / sizeof((x)[0]))
+
+/* Export Graphic Device */
+GraphicDevice smi;
+
+#define GLAMO_REG(x)	(*(volatile unsigned short *)(CONFIG_GLAMO_BASE + x))
+
+static inline void glamo_reg_write(u_int16_t reg, u_int16_t val)
+{
+	GLAMO_REG(reg) = val;
+}
+
+static inline u_int16_t glamo_reg_read(u_int16_t reg)
+{
+	return GLAMO_REG(reg);
+}
+
+struct glamo_script {
+	u_int16_t reg;
+	u_int16_t val;
+}; // __attribute__((packed));
+
+/* from 'initial glamo 3365 script' */
+static struct glamo_script gl3362_init_script[] = {
+	/* clock */
+	{ GLAMO_REG_CLOCK_MEMORY, 	0x300a },
+	{ GLAMO_REG_CLOCK_LCD,		0x10aa },
+	{ GLAMO_REG_CLOCK_MMC,		0x100a },
+	{ GLAMO_REG_CLOCK_ISP,		0x32aa },
+	{ GLAMO_REG_CLOCK_JPEG,		0x100a },
+	{ GLAMO_REG_CLOCK_3D,		0x302a },
+	{ GLAMO_REG_CLOCK_2D,		0x302a },
+	//{ GLAMO_REG_CLOCK_RISC1,	0x1aaa },
+	//{ GLAMO_REG_CLOCK_RISC2,	0x002a },
+	{ GLAMO_REG_CLOCK_MPEG,		0x3aaa },
+	{ GLAMO_REG_CLOCK_MPROC,	0x12aa },
+		{ 0xfffe, 5 },
+	{ GLAMO_REG_CLOCK_HOST,		0x000d },
+	{ GLAMO_REG_CLOCK_MEMORY,	0x000a },
+	{ GLAMO_REG_CLOCK_LCD,		0x00ee },
+	{ GLAMO_REG_CLOCK_MMC,		0x000a },
+	{ GLAMO_REG_CLOCK_ISP,		0x02aa },
+	{ GLAMO_REG_CLOCK_JPEG,		0x000a },
+	{ GLAMO_REG_CLOCK_3D,		0x002a },
+	{ GLAMO_REG_CLOCK_2D,		0x002a },
+	//{ GLAMO_REG_CLOCK_RISC1,	0x0aaa },
+	//{ GLAMO_REG_CLOCK_RISC2,	0x002a },
+	{ GLAMO_REG_CLOCK_MPEG,		0x0aaa },
+	{ GLAMO_REG_CLOCK_MPROC,	0x02aa },
+		{ 0xfffe, 5 },
+	{ GLAMO_REG_PLL_GEN1,		0x061a }, /* PLL1=50MHz, OSCI=32kHz */
+	{ GLAMO_REG_PLL_GEN3,		0x09c3 }, /* PLL2=80MHz, OSCI=32kHz */
+		{ 0xfffe, 5 },
+	{ GLAMO_REG_CLOCK_GEN5_1,	0x18ff },
+	{ GLAMO_REG_CLOCK_GEN5_2,	0x051f },
+	{ GLAMO_REG_CLOCK_GEN6,		0x2000 },
+	{ GLAMO_REG_CLOCK_GEN7,		0x0105 },
+	{ GLAMO_REG_CLOCK_GEN8,		0x0100 },
+	{ GLAMO_REG_CLOCK_GEN10,	0x0017 },
+	{ GLAMO_REG_CLOCK_GEN11,	0x0017 },
+
+	/* hostbus interface */
+	{ GLAMO_REG_HOSTBUS(1),		0x0e00 },
+	{ GLAMO_REG_HOSTBUS(2),		0x07ff },
+	{ GLAMO_REG_HOSTBUS(4),		0x0080 },
+	{ GLAMO_REG_HOSTBUS(5),		0x0244 },
+	{ GLAMO_REG_HOSTBUS(6),		0x0600 },
+	{ GLAMO_REG_HOSTBUS(12),	0xf00e },
+
+	/* memory */
+	{ GLAMO_REG_MEM_TYPE,		0x0874 }, /* VRAM 8Mbyte */
+	{ GLAMO_REG_MEM_GEN,		0xafaf },
+	{ GLAMO_REG_MEM_TIMING(1),	0x0108 },
+	{ GLAMO_REG_MEM_TIMING(2),	0x0010 },
+	{ GLAMO_REG_MEM_TIMING(3),	0x0000 },
+	{ GLAMO_REG_MEM_TIMING(4),	0x0000 },
+	{ GLAMO_REG_MEM_TIMING(5),	0x0000 },
+	{ GLAMO_REG_MEM_TIMING(6),	0x0000 },
+	{ GLAMO_REG_MEM_TIMING(7),	0x0000 },
+	{ GLAMO_REG_MEM_TIMING(8),	0x1002 },
+	{ GLAMO_REG_MEM_TIMING(9),	0x6006 },
+	{ GLAMO_REG_MEM_TIMING(10),	0x00ff },
+	{ GLAMO_REG_MEM_TIMING(11),	0x0001 },
+	{ GLAMO_REG_MEM_POWER1,		0x0020 },
+	{ GLAMO_REG_MEM_POWER2,		0x0000 },
+	{ GLAMO_REG_MEM_DRAM1,		0x0000 },
+		{ 0xfffe, 1 },
+	{ GLAMO_REG_MEM_DRAM1,		0xc100 },
+	{ GLAMO_REG_MEM_DRAM2,		0x01d6 },
+};
+
+#if 0
+static struct glamo_script gl3362_init_script[] = {
+	/* clock */
+	{ GLAMO_REG_CLOCK_MEMORY, 	0x300a },
+};
+#endif
+
+static void glamo_run_script(struct glamo_script *script, int num)
+{
+	int i;
+	for (i = 0; i < ARRAY_SIZE(gl3362_init_script); i++) {
+		struct glamo_script *reg = script + i;
+		printf("reg=0x%04x, val=0x%04x\n", reg->reg, reg->val);
+
+		if (reg->reg == 0xfffe)
+			udelay(reg->val*1000);
+		else
+			glamo_reg_write(reg->reg, reg->val);
+	}
+
+}
+
+static void glamo_core_init(void)
+{
+	printf("Glamo core device ID: 0x%04x, Revision 0x%04x\n",
+		glamo_reg_read(GLAMO_REG_DEVICE_ID),
+		glamo_reg_read(GLAMO_REG_REVISION_ID));
+
+	glamo_run_script(gl3362_init_script, ARRAY_SIZE(gl3362_init_script));
+}
+
+void *video_hw_init(void)
+{
+	u_int16_t reg;
+	GraphicDevice *pGD = (GraphicDevice *)&smi;
+
+	glamo_core_init();
+
+	printf("Video: ");
+
+	/* FIXME: returning since vram access still locks up system */
+	return NULL;
+
+	/* FIXME: this is static */
+	pGD->winSizeX = pGD->plnSizeX = 480;
+	pGD->winSizeY = pGD->plnSizeY = 640;
+	pGD->gdfBytesPP = 2;
+	pGD->gdfIndex = GDF_16BIT_565RGB;
+
+	pGD->frameAdrs = CONFIG_GLAMO_BASE + 0x00800000;
+	pGD->memSize = 0x200000; /* 480x640x16bit = 614400 bytes */
+
+	//printf("memset ");
+	//memset(pGD->frameAdrs, 0, pGD->memSize);
+
+	printf("END\n");
+
+	return &smi;
+}
+
+void
+video_set_lut(unsigned int index, unsigned char r,
+	      unsigned char g, unsigned char b)
+{
+	/* FIXME: we don't support any palletized formats */
+}
+
+#endif /* CONFIG_VIDEO_GLAMO3362 */
Index: u-boot/drivers/video/Makefile
===================================================================
--- u-boot.orig/drivers/video/Makefile
+++ u-boot/drivers/video/Makefile
@@ -33,6 +33,7 @@
 COBJS-y += sed13806.o
 COBJS-y += sed156x.o
 COBJS-y += sm501.o
+COBJS-y += smedia3362.o
 COBJS-y += smiLynxEM.o
 COBJS-y += videomodes.o
 
Index: u-boot/drivers/misc/Makefile
===================================================================
--- u-boot.orig/drivers/misc/Makefile
+++ u-boot/drivers/misc/Makefile
@@ -28,6 +28,7 @@
 COBJS-y += ali512x.o
 COBJS-y += ns87308.o
 COBJS-y += pcf50606.o
+COBJS-y += pcf50633.o
 COBJS-y += status_led.o
 COBJS-$(CONFIG_FSL_LAW) += fsl_law.o
 
Index: u-boot/common/cmd_nand.c
===================================================================
--- u-boot.orig/common/cmd_nand.c
+++ u-boot/common/cmd_nand.c
@@ -204,8 +204,10 @@
 		putc('\n');
 		for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) {
 			if (nand_info[i].name)
-				printf("Device %d: %s, sector size %lu KiB\n",
+				printf("Device %d: %s, page size %lu, "
+					"sector size %lu KiB\n",
 					i, nand_info[i].name,
+					nand_info[i].oobblock,
 					nand_info[i].erasesize >> 10);
 		}
 		return 0;
Index: u-boot/drivers/mtd/nand/nand_ids.c
===================================================================
--- u-boot.orig/drivers/mtd/nand/nand_ids.c
+++ u-boot/drivers/mtd/nand/nand_ids.c
@@ -67,7 +67,7 @@
 
 	{"NAND 256MiB 3,3V 8-bit", 	0x71, 512, 256, 0x4000, 0},
 
-	{"NAND 512MiB 3,3V 8-bit", 	0xDC, 512, 512, 0x4000, 0},
+	//{"NAND 512MiB 3,3V 8-bit", 	0xDC, 512, 512, 0x4000, 0},
 
 	/* These are the new chips with large page size. The pagesize
 	* and the erasesize is determined from the extended id bytes
Index: u-boot/board/neo1973/common/udc.c
===================================================================
--- u-boot.orig/board/neo1973/common/udc.c
+++ u-boot/board/neo1973/common/udc.c
@@ -3,6 +3,7 @@
 #include <usbdcore.h>
 #include <s3c2410.h>
 #include <pcf50606.h>
+#include <pcf50633.h>
 
 void udc_ctrl(enum usbd_event event, int param)
 {
@@ -11,7 +12,8 @@
 	switch (event) {
 	case UDC_CTRL_PULLUP_ENABLE:
 #if defined(CONFIG_ARCH_GTA01_v4) || defined(CONFIG_ARCH_GTA01B_v2) || \
-    defined(CONFIG_ARCH_GTA01B_v3) || defined(CONFIG_ARCH_GTA01B_v4)
+    defined(CONFIG_ARCH_GTA01B_v3) || defined(CONFIG_ARCH_GTA01B_v4) || \
+    defined(CONFIG_GTA02_REVISION)
 		if (param)
 			gpio->GPBDAT |= (1 << 9);
 		else
@@ -23,6 +25,11 @@
     defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3) || \
     defined(CONFIG_ARCH_GTA01B_v4)
 		pcf50606_charge_autofast(param);
+#elif defined(CONFIG_GTA02_REVISION)
+		if (param)
+			pcf50633_usb_maxcurrent(500);
+		else
+			pcf50633_usb_maxcurrent(0);
 #endif
 		break;
 	default:
Index: u-boot/drivers/video/smedia3362.h
===================================================================
--- /dev/null
+++ u-boot/drivers/video/smedia3362.h
@@ -0,0 +1,385 @@
+#ifndef _GLAMO_REGS_H
+#define _GLAMO_REGS_H
+
+/* Smedia Glamo 336x/337x driver
+ *
+ * (C) 2007 by OpenMoko, Inc.
+ * Author: Harald Welte <[e-mail]>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+enum glamo_regster_offsets {
+	GLAMO_REGOFS_GENERIC	= 0x0000,
+	GLAMO_REGOFS_HOSTBUS	= 0x0200,
+	GLAMO_REGOFS_MEMORY	= 0x0300,
+	GLAMO_REGOFS_VIDCAP	= 0x0400,
+	GLAMO_REGOFS_ISP	= 0x0500,
+	GLAMO_REGOFS_JPEG	= 0x0800,
+	GLAMO_REGOFS_MPEG	= 0x0c00,
+	GLAMO_REGOFS_LCD	= 0x1100,
+	GLAMO_REGOFS_MMC	= 0x1400,
+	GLAMO_REGOFS_MPROC0	= 0x1500,
+	GLAMO_REGOFS_MPROC1	= 0x1580,
+	GLAMO_REGOFS_CMDQUEUE	= 0x1600,
+	GLAMO_REGOFS_RISC	= 0x1680,
+	GLAMO_REGOFS_2D		= 0x1700,
+	GLAMO_REGOFS_3D		= 0x1b00,
+};
+
+
+enum glamo_register_generic {
+	GLAMO_REG_GCONF1	= 0x0000,
+	GLAMO_REG_GCONF2	= 0x0002,
+#define	GLAMO_REG_DEVICE_ID	GLAMO_REG_GCONF2
+	GLAMO_REG_GCONF3	= 0x0004,
+#define	GLAMO_REG_REVISION_ID	GLAMO_REG_GCONF3
+	GLAMO_REG_IRQ_GEN1	= 0x0006,
+#define GLAMO_REG_IRQ_ENABLE	GLAMO_REG_IRQ_GEN1
+	GLAMO_REG_IRQ_GEN2	= 0x0008,
+#define GLAMO_REG_IRQ_SET	GLAMO_REG_IRQ_GEN2
+	GLAMO_REG_IRQ_GEN3	= 0x000a,
+#define GLAMO_REG_IRQ_CLEAR	GLAMO_REG_IRQ_GEN3
+	GLAMO_REG_IRQ_GEN4	= 0x000c,
+#define GLAMO_REG_IRQ_STATUS	GLAMO_REG_IRQ_GEN4
+	GLAMO_REG_CLOCK_HOST	= 0x0010,
+	GLAMO_REG_CLO