main.tan.qmsg

直流电动机控制系统的FPGA的设计与实现。

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "Data_drive:inst\|Adc_SCL " "Info: Detected gated clock \"Data_drive:inst\|Adc_SCL\" as buffer" {  } { { "Data_drive.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/Data_drive.v" 14 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "Data_drive:inst\|Adc_SCL" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "Data_drive:inst\|Adc_SCL_Select " "Info: Detected ripple clock \"Data_drive:inst\|Adc_SCL_Select\" as buffer" {  } { { "Data_drive.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/Data_drive.v" 58 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "Data_drive:inst\|Adc_SCL_Select" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clk_SCL register Data_Read:inst1\|lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] register Data_Read:inst1\|Data\[8\] 217.39 MHz 4.6 ns Internal " "Info: Clock \"Clk_SCL\" has Internal fmax of 217.39 MHz between source register \"Data_Read:inst1\|lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]\" and destination register \"Data_Read:inst1\|Data\[8\]\" (period= 4.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.500 ns + Longest register register " "Info: + Longest register to register delay is 2.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Data_Read:inst1\|lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 1 REG LC5_A3 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_A3; Fanout = 15; REG Node = 'Data_Read:inst1\|lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/" "" "" { Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(1.100 ns) 1.500 ns Data_Read:inst1\|Decoder~25 2 COMB LC1_A2 1 " "Info: 2: + IC(0.400 ns) + CELL(1.100 ns) = 1.500 ns; Loc. = LC1_A2; Fanout = 1; COMB Node = 'Data_Read:inst1\|Decoder~25'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/" "" "1.500 ns" { Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] Data_Read:inst1|Decoder~25 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.600 ns) 2.500 ns Data_Read:inst1\|Data\[8\] 3 REG LC3_A1 1 " "Info: 3: + IC(0.400 ns) + CELL(0.600 ns) = 2.500 ns; Loc. = LC3_A1; Fanout = 1; REG Node = 'Data_Read:inst1\|Data\[8\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/" "" "1.000 ns" { Data_Read:inst1|Decoder~25 Data_Read:inst1|Data[8] } "NODE_NAME" } "" } } { "Data_Read.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/Data_Read.v" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.700 ns 68.00 % " "Info: Total cell delay = 1.700 ns ( 68.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.800 ns 32.00 % " "Info: Total interconnect delay = 0.800 ns ( 32.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/" "" "2.500 ns" { Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] Data_Read:inst1|Decoder~25 Data_Read:inst1|Data[8] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.500 ns" { Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] Data_Read:inst1|Decoder~25 Data_Read:inst1|Data[8] } { 0.000ns 0.400ns 0.400ns } { 0.000ns 1.100ns 0.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-1.400 ns - Smallest " "Info: - Smallest clock skew is -1.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk_SCL destination 4.200 ns + Shortest register " "Info: + Shortest clock path from clock \"Clk_SCL\" to destination register is 4.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Clk_SCL 1 CLK PIN_39 9 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 9; CLK Node = 'Clk_SCL'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/" "" "" { Clk_SCL } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/main.bdf" { { 336 -40 128 352 "Clk_SCL" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 2.100 ns Data_drive:inst\|Adc_SCL 2 COMB LC1_C2 20 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 2.100 ns; Loc. = LC1_C2; Fanout = 20; COMB Node = 'Data_drive:inst\|Adc_SCL'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/" "" "0.800 ns" { Clk_SCL Data_drive:inst|Adc_SCL } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/Data_drive.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(0.000 ns) 4.200 ns Data_Read:inst1\|Data\[8\] 3 REG LC3_A1 1 " "Info: 3: + IC(2.100 ns) + CELL(0.000 ns) = 4.200 ns; Loc. = LC3_A1; Fanout = 1; REG Node = 'Data_Read:inst1\|Data\[8\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/" "" "2.100 ns" { Data_drive:inst|Adc_SCL Data_Read:inst1|Data[8] } "NODE_NAME" } "" } } { "Data_Read.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/Data_Read.v" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.100 ns 50.00 % " "Info: Total cell delay = 2.100 ns ( 50.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.100 ns 50.00 % " "Info: Total interconnect delay = 2.100 ns ( 50.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/" "" "4.200 ns" { Clk_SCL Data_drive:inst|Adc_SCL Data_Read:inst1|Data[8] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.200 ns" { Clk_SCL Clk_SCL~out Data_drive:inst|Adc_SCL Data_Read:inst1|Data[8] } { 0.000ns 0.000ns 0.000ns 2.100ns } { 0.000ns 1.300ns 0.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk_SCL source 5.600 ns - Longest register " "Info: - Longest clock path from clock \"Clk_SCL\" to source register is 5.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Clk_SCL 1 CLK PIN_39 9 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 9; CLK Node = 'Clk_SCL'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/" "" "" { Clk_SCL } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/main.bdf" { { 336 -40 128 352 "Clk_SCL" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.300 ns) 1.800 ns Data_drive:inst\|Adc_SCL_Select 2 REG LC8_C1 1 " "Info: 2: + IC(0.200 ns) + CELL(0.300 ns) = 1.800 ns; Loc. = LC8_C1; Fanout = 1; REG Node = 'Data_drive:inst\|Adc_SCL_Select'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/" "" "0.500 ns" { Clk_SCL Data_drive:inst|Adc_SCL_Select } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/Data_drive.v" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(1.000 ns) 3.500 ns Data_drive:inst\|Adc_SCL 3 COMB LC1_C2 20 " "Info: 3: + IC(0.700 ns) + CELL(1.000 ns) = 3.500 ns; Loc. = LC1_C2; Fanout = 20; COMB Node = 'Data_drive:inst\|Adc_SCL'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/" "" "1.700 ns" { Data_drive:inst|Adc_SCL_Select Data_drive:inst|Adc_SCL } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/Data_drive.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(0.000 ns) 5.600 ns Data_Read:inst1\|lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 4 REG LC5_A3 15 " "Info: 4: + IC(2.100 ns) + CELL(0.000 ns) = 5.600 ns; Loc. = LC5_A3; Fanout = 15; REG Node = 'Data_Read:inst1\|lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/" "" "2.100 ns" { Data_drive:inst|Adc_SCL Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 46.43 % " "Info: Total cell delay = 2.600 ns ( 46.43 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 53.57 % " "Info: Total interconnect delay = 3.000 ns ( 53.57 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/" "" "5.600 ns" { Clk_SCL Data_drive:inst|Adc_SCL_Select Data_drive:inst|Adc_SCL Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.600 ns" { Clk_SCL Clk_SCL~out Data_drive:inst|Adc_SCL_Select Data_drive:inst|Adc_SCL Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 0.200ns 0.700ns 2.100ns } { 0.000ns 1.300ns 0.300ns 1.000ns 0.000ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/" "" "4.200 ns" { Clk_SCL Data_drive:inst|Adc_SCL Data_Read:inst1|Data[8] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.200 ns" { Clk_SCL Clk_SCL~out Data_drive:inst|Adc_SCL Data_Read:inst1|Data[8] } { 0.000ns 0.000ns 0.000ns 2.100ns } { 0.000ns 1.300ns 0.800ns 0.000ns } } } { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/" "" "5.600 ns" { Clk_SCL Data_drive:inst|Adc_SCL_Select Data_drive:inst|Adc_SCL Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.600 ns" { Clk_SCL Clk_SCL~out Data_drive:inst|Adc_SCL_Select Data_drive:inst|Adc_SCL Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 0.200ns 0.700ns 2.100ns } { 0.000ns 1.300ns 0.300ns 1.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.300 ns + " "Info: + Micro clock to output delay of source is 0.300 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.400 ns + " "Info: + Micro setup delay of destination is 0.400 ns" {  } { { "Data_Read.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/Data_Read.v" 27 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/" "" "2.500 ns" { Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] Data_Read:inst1|Decoder~25 Data_Read:inst1|Data[8] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.500 ns" { Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] Data_Read:inst1|Decoder~25 Data_Read:inst1|Data[8] } { 0.000ns 0.400ns 0.400ns } { 0.000ns 1.100ns 0.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/" "" "4.200 ns" { Clk_SCL Data_drive:inst|Adc_SCL Data_Read:inst1|Data[8] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.200 ns" { Clk_SCL Clk_SCL~out Data_drive:inst|Adc_SCL Data_Read:inst1|Data[8] } { 0.000ns 0.000ns 0.000ns 2.100ns } { 0.000ns 1.300ns 0.800ns 0.000ns } } } { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/" "" "5.600 ns" { Clk_SCL Data_drive:inst|Adc_SCL_Select Data_drive:inst|Adc_SCL Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.600 ns" { Clk_SCL Clk_SCL~out Data_drive:inst|Adc_SCL_Select Data_drive:inst|Adc_SCL Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 0.200ns 0.700ns 2.100ns } { 0.000ns 1.300ns 0.300ns 1.000ns 0.000ns } } }  } 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "Clk_SCL 10 " "Warning: Circuit may not operate. Detected 10 non-operational path(s) clocked by clock \"Clk_SCL\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}