sample_ctrl.tan.qmsg

直流电动机控制系统的FPGA的设计与实现。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Aug 03 16:06:57 2006 " "Info: Processing started: Thu Aug 03 16:06:57 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off Sample_Ctrl -c Sample_Ctrl " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off Sample_Ctrl -c Sample_Ctrl" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "Adc_Busy Sample_Ctrl_out 6.900 ns Longest " "Info: Longest tpd from source pin \"Adc_Busy\" to destination pin \"Sample_Ctrl_out\" is 6.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Adc_Busy 1 PIN PIN_91 1 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_91; Fanout = 1; PIN Node = 'Adc_Busy'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Sample_Ctrl/db/Sample_Ctrl_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Sample_Ctrl/db/Sample_Ctrl_cmp.qrpt" Compiler "Sample_Ctrl" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Sample_Ctrl/db/Sample_Ctrl.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Sample_Ctrl/" "" "" { Adc_Busy } "NODE_NAME" } "" } } { "Sample_Ctrl.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Sample_Ctrl/Sample_Ctrl.v" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.000 ns) 2.600 ns Sample_Ctrl_out~15 2 COMB LC2_A17 1 " "Info: 2: + IC(0.300 ns) + CELL(1.000 ns) = 2.600 ns; Loc. = LC2_A17; Fanout = 1; COMB Node = 'Sample_Ctrl_out~15'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Sample_Ctrl/db/Sample_Ctrl_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Sample_Ctrl/db/Sample_Ctrl_cmp.qrpt" Compiler "Sample_Ctrl" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Sample_Ctrl/db/Sample_Ctrl.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Sample_Ctrl/" "" "1.300 ns" { Adc_Busy Sample_Ctrl_out~15 } "NODE_NAME" } "" } } { "Sample_Ctrl.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Sample_Ctrl/Sample_Ctrl.v" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(3.800 ns) 6.900 ns Sample_Ctrl_out 3 PIN PIN_6 0 " "Info: 3: + IC(0.500 ns) + CELL(3.800 ns) = 6.900 ns; Loc. = PIN_6; Fanout = 0; PIN Node = 'Sample_Ctrl_out'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Sample_Ctrl/db/Sample_Ctrl_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Sample_Ctrl/db/Sample_Ctrl_cmp.qrpt" Compiler "Sample_Ctrl" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Sample_Ctrl/db/Sample_Ctrl.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Sample_Ctrl/" "" "4.300 ns" { Sample_Ctrl_out~15 Sample_Ctrl_out } "NODE_NAME" } "" } } { "Sample_Ctrl.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Sample_Ctrl/Sample_Ctrl.v" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.100 ns 88.41 % " "Info: Total cell delay = 6.100 ns ( 88.41 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.800 ns 11.59 % " "Info: Total interconnect delay = 0.800 ns ( 11.59 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Sample_Ctrl/db/Sample_Ctrl_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Sample_Ctrl/db/Sample_Ctrl_cmp.qrpt" Compiler "Sample_Ctrl" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Sample_Ctrl/db/Sample_Ctrl.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Sample_Ctrl/" "" "6.900 ns" { Adc_Busy Sample_Ctrl_out~15 Sample_Ctrl_out } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.900 ns" { Adc_Busy Adc_Busy~out Sample_Ctrl_out~15 Sample_Ctrl_out } { 0.000ns 0.000ns 0.300ns 0.500ns } { 0.000ns 1.300ns 1.000ns 3.800ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Aug 03 16:06:58 2006 " "Info: Processing ended: Thu Aug 03 16:06:58 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}