pulse_16_sum.v

步进电机位置控制系统的FPGA设计与实现。

// Copyright (C) 1991-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
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module pulse_16_sum(
	Clk_65536Hz,
	Reset,
	counter_data,
	second_pulse_data,
	pulse_out
);

input	Clk_65536Hz;
input	Reset;
input	[15:0] counter_data;
input	[15:0] second_pulse_data;
output	pulse_out;

wire	[15:0] SYNTHESIZED_WIRE_0;





pulse_16	b2v_inst(.Reset(Reset),
.counter_data(counter_data),.pulse_16_out(SYNTHESIZED_WIRE_0));

pulse_sum	b2v_inst1(.Reset(Reset),
.Clock_65536Hz(Clk_65536Hz),.pulse_16_data(SYNTHESIZED_WIRE_0),.second_pulse_data(second_pulse_data),.pulse_out(pulse_out));


endmodule