sum_control.tan.qmsg

步进电机位置控制系统的FPGA设计与实现。

{ "Info" "ITDB_TH_RESULT" "lpm_counter:step_counter_rtl_0\|dffs\[0\] Reset pulse_sum_in -1.300 ns register " "Info: th for register \"lpm_counter:step_counter_rtl_0\|dffs\[0\]\" (data pin = \"Reset\", clock pin = \"pulse_sum_in\") is -1.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pulse_sum_in destination 2.200 ns + Longest register " "Info: + Longest clock path from clock \"pulse_sum_in\" to destination register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns pulse_sum_in 1 CLK PIN_83 26 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 26; CLK Node = 'pulse_sum_in'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "" { pulse_sum_in } "NODE_NAME" } "" } } { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/sum_control.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.200 ns lpm_counter:step_counter_rtl_0\|dffs\[0\] 2 REG LC70 27 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC70; Fanout = 27; REG Node = 'lpm_counter:step_counter_rtl_0\|dffs\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "0.600 ns" { pulse_sum_in lpm_counter:step_counter_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "2.200 ns" { pulse_sum_in lpm_counter:step_counter_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { pulse_sum_in pulse_sum_in~out lpm_counter:step_counter_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.700 ns + " "Info: + Micro hold delay of destination is 1.700 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.200 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns Reset 1 PIN PIN_81 95 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_81; Fanout = 95; PIN Node = 'Reset'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "" { Reset } "NODE_NAME" } "" } } { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/sum_control.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(3.000 ns) 5.200 ns lpm_counter:step_counter_rtl_0\|dffs\[0\] 2 REG LC70 27 " "Info: 2: + IC(2.000 ns) + CELL(3.000 ns) = 5.200 ns; Loc. = LC70; Fanout = 27; REG Node = 'lpm_counter:step_counter_rtl_0\|dffs\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "5.000 ns" { Reset lpm_counter:step_counter_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns 61.54 % " "Info: Total cell delay = 3.200 ns ( 61.54 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 38.46 % " "Info: Total interconnect delay = 2.000 ns ( 38.46 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "5.200 ns" { Reset lpm_counter:step_counter_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.200 ns" { Reset Reset~out lpm_counter:step_counter_rtl_0|dffs[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 0.200ns 3.000ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "2.200 ns" { pulse_sum_in lpm_counter:step_counter_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { pulse_sum_in pulse_sum_in~out lpm_counter:step_counter_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "5.200 ns" { Reset lpm_counter:step_counter_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.200 ns" { Reset Reset~out lpm_counter:step_counter_rtl_0|dffs[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 0.200ns 3.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 20 23:54:22 2006 " "Info: Processing ended: Thu Jul 20 23:54:22 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}