📄 sum_control.tan.qmsg
字号:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "pulse_sum_in " "Info: Assuming node \"pulse_sum_in\" is an undefined clock" { } { { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/sum_control.v" 11 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum_in" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "pulse_sum_in register lpm_counter:step_counter_rtl_0\|dffs\[4\] register out_control 54.35 MHz 18.4 ns Internal " "Info: Clock \"pulse_sum_in\" has Internal fmax of 54.35 MHz between source register \"lpm_counter:step_counter_rtl_0\|dffs\[4\]\" and destination register \"out_control\" (period= 18.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.000 ns + Longest register register " "Info: + Longest register to register delay is 16.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:step_counter_rtl_0\|dffs\[4\] 1 REG LC117 26 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC117; Fanout = 26; REG Node = 'lpm_counter:step_counter_rtl_0\|dffs\[4\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "" { lpm_counter:step_counter_rtl_0|dffs[4] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(4.000 ns) 5.700 ns always0~217sexppiapart 2 COMB LC81 45 " "Info: 2: + IC(1.700 ns) + CELL(4.000 ns) = 5.700 ns; Loc. = LC81; Fanout = 45; COMB Node = 'always0~217sexppiapart'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "5.700 ns" { lpm_counter:step_counter_rtl_0|dffs[4] always0~217sexppiapart } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(4.000 ns) 11.600 ns out_control~piapart 3 COMB LC23 1 " "Info: 3: + IC(1.900 ns) + CELL(4.000 ns) = 11.600 ns; Loc. = LC23; Fanout = 1; COMB Node = 'out_control~piapart'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "5.900 ns" { always0~217sexppiapart out_control~piapart } "NODE_NAME" } "" } } { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/sum_control.v" 37 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(3.000 ns) 16.000 ns out_control 4 REG LC19 2 " "Info: 4: + IC(1.400 ns) + CELL(3.000 ns) = 16.000 ns; Loc. = LC19; Fanout = 2; REG Node = 'out_control'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "4.400 ns" { out_control~piapart out_control } "NODE_NAME" } "" } } { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/sum_control.v" 37 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.000 ns 68.75 % " "Info: Total cell delay = 11.000 ns ( 68.75 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.000 ns 31.25 % " "Info: Total interconnect delay = 5.000 ns ( 31.25 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "16.000 ns" { lpm_counter:step_counter_rtl_0|dffs[4] always0~217sexppiapart out_control~piapart out_control } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "16.000 ns" { lpm_counter:step_counter_rtl_0|dffs[4] always0~217sexppiapart out_control~piapart out_control } { 0.000ns 1.700ns 1.900ns 1.400ns } { 0.000ns 4.000ns 4.000ns 3.000ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pulse_sum_in destination 2.200 ns + Shortest register " "Info: + Shortest clock path from clock \"pulse_sum_in\" to destination register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns pulse_sum_in 1 CLK PIN_83 26 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 26; CLK Node = 'pulse_sum_in'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "" { pulse_sum_in } "NODE_NAME" } "" } } { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/sum_control.v" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.200 ns out_control 2 REG LC19 2 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC19; Fanout = 2; REG Node = 'out_control'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "0.600 ns" { pulse_sum_in out_control } "NODE_NAME" } "" } } { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/sum_control.v" 37 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "2.200 ns" { pulse_sum_in out_control } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { pulse_sum_in pulse_sum_in~out out_control } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pulse_sum_in source 2.200 ns - Longest register " "Info: - Longest clock path from clock \"pulse_sum_in\" to source register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns pulse_sum_in 1 CLK PIN_83 26 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 26; CLK Node = 'pulse_sum_in'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "" { pulse_sum_in } "NODE_NAME" } "" } } { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/sum_control.v" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.200 ns lpm_counter:step_counter_rtl_0\|dffs\[4\] 2 REG LC117 26 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC117; Fanout = 26; REG Node = 'lpm_counter:step_counter_rtl_0\|dffs\[4\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "0.600 ns" { pulse_sum_in lpm_counter:step_counter_rtl_0|dffs[4] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "2.200 ns" { pulse_sum_in lpm_counter:step_counter_rtl_0|dffs[4] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { pulse_sum_in pulse_sum_in~out lpm_counter:step_counter_rtl_0|dffs[4] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "2.200 ns" { pulse_sum_in out_control } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { pulse_sum_in pulse_sum_in~out out_control } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "2.200 ns" { pulse_sum_in lpm_counter:step_counter_rtl_0|dffs[4] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { pulse_sum_in pulse_sum_in~out lpm_counter:step_counter_rtl_0|dffs[4] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.400 ns + " "Info: + Micro clock to output delay of source is 1.400 ns" { } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.000 ns + " "Info: + Micro setup delay of destination is 1.000 ns" { } { { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/sum_control.v" 37 -1 0 } } } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "16.000 ns" { lpm_counter:step_counter_rtl_0|dffs[4] always0~217sexppiapart out_control~piapart out_control } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "16.000 ns" { lpm_counter:step_counter_rtl_0|dffs[4] always0~217sexppiapart out_control~piapart out_control } { 0.000ns 1.700ns 1.900ns 1.400ns } { 0.000ns 4.000ns 4.000ns 3.000ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "2.200 ns" { pulse_sum_in out_control } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { pulse_sum_in pulse_sum_in~out out_control } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "2.200 ns" { pulse_sum_in lpm_counter:step_counter_rtl_0|dffs[4] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { pulse_sum_in pulse_sum_in~out lpm_counter:step_counter_rtl_0|dffs[4] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "out_control step_sum\[8\] pulse_sum_in 14.700 ns register " "Info: tsu for register \"out_control\" (data pin = \"step_sum\[8\]\", clock pin = \"pulse_sum_in\") is 14.700 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "15.900 ns + Longest pin register " "Info: + Longest pin to register delay is 15.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns step_sum\[8\] 1 PIN PIN_57 1 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_57; Fanout = 1; PIN Node = 'step_sum\[8\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "" { step_sum[8] } "NODE_NAME" } "" } } { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/sum_control.v" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(4.000 ns) 5.600 ns always0~237 2 COMB LC99 45 " "Info: 2: + IC(1.400 ns) + CELL(4.000 ns) = 5.600 ns; Loc. = LC99; Fanout = 45; COMB Node = 'always0~237'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "5.400 ns" { step_sum[8] always0~237 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(4.000 ns) 11.500 ns out_control~piapart 3 COMB LC23 1 " "Info: 3: + IC(1.900 ns) + CELL(4.000 ns) = 11.500 ns; Loc. = LC23; Fanout = 1; COMB Node = 'out_control~piapart'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "5.900 ns" { always0~237 out_control~piapart } "NODE_NAME" } "" } } { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/sum_control.v" 37 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(3.000 ns) 15.900 ns out_control 4 REG LC19 2 " "Info: 4: + IC(1.400 ns) + CELL(3.000 ns) = 15.900 ns; Loc. = LC19; Fanout = 2; REG Node = 'out_control'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "4.400 ns" { out_control~piapart out_control } "NODE_NAME" } "" } } { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/sum_control.v" 37 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.200 ns 70.44 % " "Info: Total cell delay = 11.200 ns ( 70.44 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.700 ns 29.56 % " "Info: Total interconnect delay = 4.700 ns ( 29.56 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "15.900 ns" { step_sum[8] always0~237 out_control~piapart out_control } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "15.900 ns" { step_sum[8] step_sum[8]~out always0~237 out_control~piapart out_control } { 0.000ns 0.000ns 1.400ns 1.900ns 1.400ns } { 0.000ns 0.200ns 4.000ns 4.000ns 3.000ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.000 ns + " "Info: + Micro setup delay of destination is 1.000 ns" { } { { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/sum_control.v" 37 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pulse_sum_in destination 2.200 ns - Shortest register " "Info: - Shortest clock path from clock \"pulse_sum_in\" to destination register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns pulse_sum_in 1 CLK PIN_83 26 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 26; CLK Node = 'pulse_sum_in'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "" { pulse_sum_in } "NODE_NAME" } "" } } { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/sum_control.v" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.200 ns out_control 2 REG LC19 2 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC19; Fanout = 2; REG Node = 'out_control'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "0.600 ns" { pulse_sum_in out_control } "NODE_NAME" } "" } } { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/sum_control.v" 37 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "2.200 ns" { pulse_sum_in out_control } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { pulse_sum_in pulse_sum_in~out out_control } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "15.900 ns" { step_sum[8] always0~237 out_control~piapart out_control } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "15.900 ns" { step_sum[8] step_sum[8]~out always0~237 out_control~piapart out_control } { 0.000ns 0.000ns 1.400ns 1.900ns 1.400ns } { 0.000ns 0.200ns 4.000ns 4.000ns 3.000ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "2.200 ns" { pulse_sum_in out_control } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { pulse_sum_in pulse_sum_in~out out_control } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "pulse_sum_in wave_out out_control 9.500 ns register " "Info: tco from clock \"pulse_sum_in\" to destination pin \"wave_out\" through register \"out_control\" is 9.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pulse_sum_in source 2.200 ns + Longest register " "Info: + Longest clock path from clock \"pulse_sum_in\" to source register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns pulse_sum_in 1 CLK PIN_83 26 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 26; CLK Node = 'pulse_sum_in'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "" { pulse_sum_in } "NODE_NAME" } "" } } { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/sum_control.v" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.200 ns out_control 2 REG LC19 2 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC19; Fanout = 2; REG Node = 'out_control'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "0.600 ns" { pulse_sum_in out_control } "NODE_NAME" } "" } } { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/sum_control.v" 37 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "2.200 ns" { pulse_sum_in out_control } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { pulse_sum_in pulse_sum_in~out out_control } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.400 ns + " "Info: + Micro clock to output delay of source is 1.400 ns" { } { { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/sum_control.v" 37 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.900 ns + Longest register pin " "Info: + Longest register to pin delay is 5.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns out_control 1 REG LC19 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC19; Fanout = 2; REG Node = 'out_control'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "" { out_control } "NODE_NAME" } "" } } { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/sum_control.v" 37 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(4.000 ns) 5.500 ns wave_out~9 2 COMB LC97 1 " "Info: 2: + IC(1.500 ns) + CELL(4.000 ns) = 5.500 ns; Loc. = LC97; Fanout = 1; COMB Node = 'wave_out~9'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "5.500 ns" { out_control wave_out~9 } "NODE_NAME" } "" } } { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/sum_control.v" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 5.900 ns wave_out 3 PIN PIN_63 0 " "Info: 3: + IC(0.000 ns) + CELL(0.400 ns) = 5.900 ns; Loc. = PIN_63; Fanout = 0; PIN Node = 'wave_out'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "0.400 ns" { wave_out~9 wave_out } "NODE_NAME" } "" } } { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/sum_control.v" 8 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.400 ns 74.58 % " "Info: Total cell delay = 4.400 ns ( 74.58 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.500 ns 25.42 % " "Info: Total interconnect delay = 1.500 ns ( 25.42 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "5.900 ns" { out_control wave_out~9 wave_out } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.900 ns" { out_control wave_out~9 wave_out } { 0.000ns 1.500ns 0.000ns } { 0.000ns 4.000ns 0.400ns } } } } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "2.200 ns" { pulse_sum_in out_control } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { pulse_sum_in pulse_sum_in~out out_control } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "5.900 ns" { out_control wave_out~9 wave_out } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.900 ns" { out_control wave_out~9 wave_out } { 0.000ns 1.500ns 0.000ns } { 0.000ns 4.000ns 0.400ns } } } } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "pulse_sum_in wave_out 6.000 ns Longest " "Info: Longest tpd from source pin \"pulse_sum_in\" to destination pin \"wave_out\" is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns pulse_sum_in 1 CLK PIN_83 26 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 26; CLK Node = 'pulse_sum_in'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "" { pulse_sum_in } "NODE_NAME" } "" } } { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/sum_control.v" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 5.600 ns wave_out~9 2 COMB LC97 1 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 5.600 ns; Loc. = LC97; Fanout = 1; COMB Node = 'wave_out~9'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "4.000 ns" { pulse_sum_in wave_out~9 } "NODE_NAME" } "" } } { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/sum_control.v" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 6.000 ns wave_out 3 PIN PIN_63 0 " "Info: 3: + IC(0.000 ns) + CELL(0.400 ns) = 6.000 ns; Loc. = PIN_63; Fanout = 0; PIN Node = 'wave_out'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "0.400 ns" { wave_out~9 wave_out } "NODE_NAME" } "" } } { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/sum_control.v" 8 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns 100.00 % " "Info: Total cell delay = 6.000 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control_cmp.qrpt" Compiler "sum_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/db/sum_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/sum_control/" "" "6.000 ns" { pulse_sum_in wave_out~9 wave_out } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.000 ns" { pulse_sum_in pulse_sum_in~out wave_out~9 wave_out } { 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 4.000ns 0.400ns } } } } 0}
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