sum_control.fit.eqn

步进电机位置控制系统的FPGA设计与实现。

B1L42_p2_out = !Reset & B1_dffs[10] & B1_dffs[9] & B1_dffs[8] & B1_dffs[7] & B1_dffs[6] & B1_dffs[5] & B1_dffs[4] & B1_dffs[3] & B1_dffs[2] & B1_dffs[0] & B1_dffs[1];
B1L42_p3_out = Reset & B1_dffs[11];
B1L42_or_out = B1L42_p2_out # B1L42_p3_out;
B1L42 = B1_dffs[11] $ B1L42_or_out;


--B1_dffs[11] is lpm_counter:step_counter_rtl_0|dffs[11] at LC114
B1_dffs[11]_p2_out = !Reset & A1L7 & !A1L01 & !A1L11 & !A1L21 & !A1L31 & !A1L41 & !A1L51 & !A1L61 & !A1L71 & !A1L81 & !A1L91 & !A1L02 & !A1L12 & !A1L22 & !A1L32 & !A1L42 & !A1L52 & B1_dffs[11] & !B1L42 & A1L6 & A1L8 & A1L9;
B1_dffs[11]_p3_out = !Reset & A1L7 & !A1L01 & !A1L11 & !A1L21 & !A1L31 & !A1L41 & !A1L51 & !A1L61 & !A1L71 & !A1L81 & !A1L91 & !A1L02 & !A1L12 & !A1L22 & !A1L32 & !A1L42 & !A1L52 & !B1_dffs[11] & B1L42 & A1L6 & A1L8 & A1L9;
B1_dffs[11]_or_out = B1_dffs[11]_p2_out # B1_dffs[11]_p3_out;
B1_dffs[11]_reg_input = B1L42 $ B1_dffs[11]_or_out;
B1_dffs[11] = DFFE(B1_dffs[11]_reg_input, GLOBAL(pulse_sum_in), , , );


--B1L62 is lpm_counter:step_counter_rtl_0|dffs[12]~1345 at LC14
B1L62_p2_out = !Reset & B1_dffs[11] & B1_dffs[10] & B1_dffs[9] & B1_dffs[8] & B1_dffs[7] & B1_dffs[6] & B1_dffs[5] & B1_dffs[4] & B1_dffs[3] & B1_dffs[2] & B1_dffs[0] & B1_dffs[1];
B1L62_p3_out = Reset & B1_dffs[12];
B1L62_or_out = B1L62_p2_out # B1L62_p3_out;
B1L62 = B1_dffs[12] $ B1L62_or_out;


--B1_dffs[12] is lpm_counter:step_counter_rtl_0|dffs[12] at LC44
B1_dffs[12]_p2_out = !Reset & A1L7 & !A1L01 & !A1L11 & !A1L21 & !A1L31 & !A1L41 & !A1L51 & !A1L61 & !A1L71 & !A1L81 & !A1L91 & !A1L02 & !A1L12 & !A1L22 & !A1L32 & !A1L42 & !A1L52 & B1_dffs[12] & !B1L62 & A1L6 & A1L8 & A1L9;
B1_dffs[12]_p3_out = !Reset & A1L7 & !A1L01 & !A1L11 & !A1L21 & !A1L31 & !A1L41 & !A1L51 & !A1L61 & !A1L71 & !A1L81 & !A1L91 & !A1L02 & !A1L12 & !A1L22 & !A1L32 & !A1L42 & !A1L52 & !B1_dffs[12] & B1L62 & A1L6 & A1L8 & A1L9;
B1_dffs[12]_or_out = B1_dffs[12]_p2_out # B1_dffs[12]_p3_out;
B1_dffs[12]_reg_input = B1L62 $ B1_dffs[12]_or_out;
B1_dffs[12] = DFFE(B1_dffs[12]_reg_input, GLOBAL(pulse_sum_in), , , );


--B1L82 is lpm_counter:step_counter_rtl_0|dffs[13]~1355 at LC11
B1L82_p2_out = !Reset & B1_dffs[12] & B1_dffs[11] & B1_dffs[10] & B1_dffs[9] & B1_dffs[8] & B1_dffs[7] & B1_dffs[6] & B1_dffs[5] & B1_dffs[4] & B1_dffs[3] & B1_dffs[2] & B1_dffs[0] & B1_dffs[1];
B1L82_p3_out = Reset & B1_dffs[13];
B1L82_or_out = B1L82_p2_out # B1L82_p3_out;
B1L82 = B1_dffs[13] $ B1L82_or_out;


--B1_dffs[13] is lpm_counter:step_counter_rtl_0|dffs[13] at LC48
B1_dffs[13]_p2_out = !Reset & A1L7 & !A1L01 & !A1L11 & !A1L21 & !A1L31 & !A1L41 & !A1L51 & !A1L61 & !A1L71 & !A1L81 & !A1L91 & !A1L02 & !A1L12 & !A1L22 & !A1L32 & !A1L42 & !A1L52 & B1_dffs[13] & !B1L82 & A1L6 & A1L8 & A1L9;
B1_dffs[13]_p3_out = !Reset & A1L7 & !A1L01 & !A1L11 & !A1L21 & !A1L31 & !A1L41 & !A1L51 & !A1L61 & !A1L71 & !A1L81 & !A1L91 & !A1L02 & !A1L12 & !A1L22 & !A1L32 & !A1L42 & !A1L52 & !B1_dffs[13] & B1L82 & A1L6 & A1L8 & A1L9;
B1_dffs[13]_or_out = B1_dffs[13]_p2_out # B1_dffs[13]_p3_out;
B1_dffs[13]_reg_input = B1L82 $ B1_dffs[13]_or_out;
B1_dffs[13] = DFFE(B1_dffs[13]_reg_input, GLOBAL(pulse_sum_in), , , );


--B1L03 is lpm_counter:step_counter_rtl_0|dffs[14]~1365 at LC1
B1L03_p2_out = !Reset & B1_dffs[13] & B1_dffs[12] & B1_dffs[11] & B1_dffs[10] & B1_dffs[9] & B1_dffs[8] & B1_dffs[7] & B1_dffs[6] & B1_dffs[5] & B1_dffs[4] & B1_dffs[3] & B1_dffs[2] & B1_dffs[0] & B1_dffs[1];
B1L03_p3_out = Reset & B1_dffs[14];
B1L03_or_out = B1L03_p2_out # B1L03_p3_out;
B1L03 = B1_dffs[14] $ B1L03_or_out;


--B1_dffs[14] is lpm_counter:step_counter_rtl_0|dffs[14] at LC33
B1_dffs[14]_p2_out = !Reset & A1L7 & !A1L01 & !A1L11 & !A1L21 & !A1L31 & !A1L41 & !A1L51 & !A1L61 & !A1L71 & !A1L81 & !A1L91 & !A1L02 & !A1L12 & !A1L22 & !A1L32 & !A1L42 & !A1L52 & B1_dffs[14] & !B1L03 & A1L6 & A1L8 & A1L9;
B1_dffs[14]_p3_out = !Reset & A1L7 & !A1L01 & !A1L11 & !A1L21 & !A1L31 & !A1L41 & !A1L51 & !A1L61 & !A1L71 & !A1L81 & !A1L91 & !A1L02 & !A1L12 & !A1L22 & !A1L32 & !A1L42 & !A1L52 & !B1_dffs[14] & B1L03 & A1L6 & A1L8 & A1L9;
B1_dffs[14]_or_out = B1_dffs[14]_p2_out # B1_dffs[14]_p3_out;
B1_dffs[14]_reg_input = B1L03 $ B1_dffs[14]_or_out;
B1_dffs[14] = DFFE(B1_dffs[14]_reg_input, GLOBAL(pulse_sum_in), , , );


--B1L23 is lpm_counter:step_counter_rtl_0|dffs[15]~1375 at LC10
B1L23_p2_out = !Reset & B1_dffs[14] & B1_dffs[13] & B1_dffs[12] & B1_dffs[11] & B1_dffs[10] & B1_dffs[9] & B1_dffs[8] & B1_dffs[7] & B1_dffs[6] & B1_dffs[5] & B1_dffs[4] & B1_dffs[3] & B1_dffs[2] & B1_dffs[0] & B1_dffs[1];
B1L23_p3_out = Reset & B1_dffs[15];
B1L23_or_out = B1L23_p2_out # B1L23_p3_out;
B1L23 = B1_dffs[15] $ B1L23_or_out;


--B1_dffs[15] is lpm_counter:step_counter_rtl_0|dffs[15] at LC121
B1_dffs[15]_p2_out = !Reset & A1L7 & !A1L01 & !A1L11 & !A1L21 & !A1L31 & !A1L41 & !A1L51 & !A1L61 & !A1L71 & !A1L81 & !A1L91 & !A1L02 & !A1L12 & !A1L22 & !A1L32 & !A1L42 & !A1L52 & B1_dffs[15] & !B1L23 & A1L6 & A1L8 & A1L9;
B1_dffs[15]_p3_out = !Reset & A1L7 & !A1L01 & !A1L11 & !A1L21 & !A1L31 & !A1L41 & !A1L51 & !A1L61 & !A1L71 & !A1L81 & !A1L91 & !A1L02 & !A1L12 & !A1L22 & !A1L32 & !A1L42 & !A1L52 & !B1_dffs[15] & B1L23 & A1L6 & A1L8 & A1L9;
B1_dffs[15]_or_out = B1_dffs[15]_p2_out # B1_dffs[15]_p3_out;
B1_dffs[15]_reg_input = B1L23 $ B1_dffs[15]_or_out;
B1_dffs[15] = DFFE(B1_dffs[15]_reg_input, GLOBAL(pulse_sum_in), , , );


--B1L43 is lpm_counter:step_counter_rtl_0|dffs[16]~1385 at LC12
B1L43_p2_out = !Reset & B1_dffs[15] & B1_dffs[14] & B1_dffs[13] & B1_dffs[12] & B1_dffs[11] & B1_dffs[10] & B1_dffs[9] & B1_dffs[8] & B1_dffs[7] & B1_dffs[6] & B1_dffs[5] & B1_dffs[4] & B1_dffs[3] & B1_dffs[2] & B1_dffs[0] & B1_dffs[1];
B1L43_p3_out = Reset & B1_dffs[16];
B1L43_or_out = B1L43_p2_out # B1L43_p3_out;
B1L43 = B1_dffs[16] $ B1L43_or_out;


--B1_dffs[16] is lpm_counter:step_counter_rtl_0|dffs[16] at LC126
B1_dffs[16]_p2_out = !Reset & A1L7 & !A1L01 & !A1L11 & !A1L21 & !A1L31 & !A1L41 & !A1L51 & !A1L61 & !A1L71 & !A1L81 & !A1L91 & !A1L02 & !A1L12 & !A1L22 & !A1L32 & !A1L42 & !A1L52 & B1_dffs[16] & !B1L43 & A1L6 & A1L8 & A1L9;
B1_dffs[16]_p3_out = !Reset & A1L7 & !A1L01 & !A1L11 & !A1L21 & !A1L31 & !A1L41 & !A1L51 & !A1L61 & !A1L71 & !A1L81 & !A1L91 & !A1L02 & !A1L12 & !A1L22 & !A1L32 & !A1L42 & !A1L52 & !B1_dffs[16] & B1L43 & A1L6 & A1L8 & A1L9;
B1_dffs[16]_or_out = B1_dffs[16]_p2_out # B1_dffs[16]_p3_out;
B1_dffs[16]_reg_input = B1L43 $ B1_dffs[16]_or_out;
B1_dffs[16] = DFFE(B1_dffs[16]_reg_input, GLOBAL(pulse_sum_in), , , );


--B1L63 is lpm_counter:step_counter_rtl_0|dffs[17]~1395 at LC16
B1L63_p2_out = !Reset & B1_dffs[16] & B1_dffs[15] & B1_dffs[14] & B1_dffs[13] & B1_dffs[12] & B1_dffs[11] & B1_dffs[10] & B1_dffs[9] & B1_dffs[8] & B1_dffs[7] & B1_dffs[6] & B1_dffs[5] & B1_dffs[4] & B1_dffs[3] & B1_dffs[2] & B1_dffs[0] & B1_dffs[1];
B1L63_p3_out = Reset & B1_dffs[17];
B1L63_or_out = B1L63_p2_out # B1L63_p3_out;
B1L63 = B1_dffs[17] $ B1L63_or_out;


--B1_dffs[17] is lpm_counter:step_counter_rtl_0|dffs[17] at LC60
B1_dffs[17]_p2_out = !Reset & A1L7 & !A1L01 & !A1L11 & !A1L21 & !A1L31 & !A1L41 & !A1L51 & !A1L61 & !A1L71 & !A1L81 & !A1L91 & !A1L02 & !A1L12 & !A1L22 & !A1L32 & !A1L42 & !A1L52 & B1_dffs[17] & !B1L63 & A1L6 & A1L8 & A1L9;
B1_dffs[17]_p3_out = !Reset & A1L7 & !A1L01 & !A1L11 & !A1L21 & !A1L31 & !A1L41 & !A1L51 & !A1L61 & !A1L71 & !A1L81 & !A1L91 & !A1L02 & !A1L12 & !A1L22 & !A1L32 & !A1L42 & !A1L52 & !B1_dffs[17] & B1L63 & A1L6 & A1L8 & A1L9;
B1_dffs[17]_or_out = B1_dffs[17]_p2_out # B1_dffs[17]_p3_out;
B1_dffs[17]_reg_input = B1L63 $ B1_dffs[17]_or_out;
B1_dffs[17] = DFFE(B1_dffs[17]_reg_input, GLOBAL(pulse_sum_in), , , );


--B1L83 is lpm_counter:step_counter_rtl_0|dffs[18]~1405 at LC15
B1L83_p2_out = !Reset & B1_dffs[17] & B1_dffs[16] & B1_dffs[15] & B1_dffs[14] & B1_dffs[13] & B1_dffs[12] & B1_dffs[11] & B1_dffs[10] & B1_dffs[9] & B1_dffs[8] & B1_dffs[7] & B1_dffs[6] & B1_dffs[5] & B1_dffs[4] & B1_dffs[3] & B1_dffs[2] & B1_dffs[0] & B1_dffs[1];
B1L83_p3_out = Reset & B1_dffs[18];
B1L83_or_out = B1L83_p2_out # B1L83_p3_out;
B1L83 = B1_dffs[18] $ B1L83_or_out;


--B1_dffs[18] is lpm_counter:step_counter_rtl_0|dffs[18] at LC64
B1_dffs[18]_p2_out = !Reset & A1L7 & !A1L01 & !A1L11 & !A1L21 & !A1L31 & !A1L41 & !A1L51 & !A1L61 & !A1L71 & !A1L81 & !A1L91 & !A1L02 & !A1L12 & !A1L22 & !A1L32 & !A1L42 & !A1L52 & B1_dffs[18] & !B1L83 & A1L6 & A1L8 & A1L9;
B1_dffs[18]_p3_out = !Reset & A1L7 & !A1L01 & !A1L11 & !A1L21 & !A1L31 & !A1L41 & !A1L51 & !A1L61 & !A1L71 & !A1L81 & !A1L91 & !A1L02 & !A1L12 & !A1L22 & !A1L32 & !A1L42 & !A1L52 & !B1_dffs[18] & B1L83 & A1L6 & A1L8 & A1L9;
B1_dffs[18]_or_out = B1_dffs[18]_p2_out # B1_dffs[18]_p3_out;
B1_dffs[18]_reg_input = B1L83 $ B1_dffs[18]_or_out;
B1_dffs[18] = DFFE(B1_dffs[18]_reg_input, GLOBAL(pulse_sum_in), , , );


--B1L04 is lpm_counter:step_counter_rtl_0|dffs[19]~1415 at LC13
B1L04_p2_out = !Reset & B1_dffs[18] & B1_dffs[17] & B1_dffs[16] & B1_dffs[15] & B1_dffs[14] & B1_dffs[13] & B1_dffs[12] & B1_dffs[11] & B1_dffs[10] & B1_dffs[9] & B1_dffs[8] & B1_dffs[7] & B1_dffs[6] & B1_dffs[5] & B1_dffs[4] & B1_dffs[3] & B1_dffs[2] & B1_dffs[0] & B1_dffs[1];
B1L04_p3_out = Reset & B1_dffs[19];
B1L04_or_out = B1L04_p2_out # B1L04_p3_out;
B1L04 = B1_dffs[19] $ B1L04_or_out;


--B1_dffs[19] is lpm_counter:step_counter_rtl_0|dffs[19] at LC54
B1_dffs[19]_p2_out = !Reset & A1L7 & !A1L01 & !A1L11 & !A1L21 & !A1L31 & !A1L41 & !A1L51 & !A1L61 & !A1L71 & !A1L81 & !A1L91 & !A1L02 & !A1L12 & !A1L22 & !A1L32 & !A1L42 & !A1L52 & B1_dffs[19] & !B1L04 & A1L6 & A1L8 & A1L9;
B1_dffs[19]_p3_out = !Reset & A1L7 & !A1L01 & !A1L11 & !A1L21 & !A1L31 & !A1L41 & !A1L51 & !A1L61 & !A1L71 & !A1L81 & !A1L91 & !A1L02 & !A1L12 & !A1L22 & !A1L32 & !A1L42 & !A1L52 & !B1_dffs[19] & B1L04 & A1L6 & A1L8 & A1L9;
B1_dffs[19]_or_out = B1_dffs[19]_p2_out # B1_dffs[19]_p3_out;
B1_dffs[19]_reg_input = B1L04 $ B1_dffs[19]_or_out;
B1_dffs[19] = DFFE(B1_dffs[19]_reg_input, GLOBAL(pulse_sum_in), , , );


--B1L24 is lpm_counter:step_counter_rtl_0|dffs[20]~1425 at LC7
B1L24_p2_out = !Reset & B1_dffs[19] & B1_dffs[18] & B1_dffs[17] & B1_dffs[16] & B1_dffs[15] & B1_dffs[14] & B1_dffs[13] & B1_dffs[12] & B1_dffs[11] & B1_dffs[10] & B1_dffs[9] & B1_dffs[8] & B1_dffs[7] & B1_dffs[6] & B1_dffs[5] & B1_dffs[4] & B1_dffs[3] & B1_dffs[2] & B1_dffs[0] & B1_dffs[1];
B1L24_p3_out = Reset & B1_dffs[20];
B1L24_or_out = B1L24_p2_out # B1L24_p3_out;
B1L24 = B1_dffs[20] $ B1L24_or_out;


--B1_dffs[20] is lpm_counter:step_counter_rtl_0|dffs[20] at LC57
B1_dffs[20]_p2_out = !Reset & A1L7 & !A1L01 & !A1L11 & !A1L21 & !A1L31 & !A1L41 & !A1L51 & !A1L61 & !A1L71 & !A1L81 & !A1L91 & !A1L02 & !A1L12 & !A1L22 & !A1L32 & !A1L42 & !A1L52 & B1_dffs[20] & !B1L24 & A1L6 & A1L8 & A1L9;
B1_dffs[20]_p3_out = !Reset & A1L7 & !A1L01 & !A1L11 & !A1L21 & !A1L31 & !A1L41 & !A1L51 & !A1L61 & !A1L71 & !A1L81 & !A1L91 & !A1L02 & !A1L12 & !A1L22 & !A1L32 & !A1L42 & !A1L52 & !B1_dffs[20] & B1L24 & A1L6 & A1L8 & A1L9;
B1_dffs[20]_or_out = B1_dffs[20]_p2_out # B1_dffs[20]_p3_out;
B1_dffs[20]_reg_input = B1L24 $ B1_dffs[20]_or_out;
B1_dffs[20] = DFFE(B1_dffs[20]_reg_input, GLOBAL(pulse_sum_in), , , );


--B1L44 is lpm_counter:step_counter_rtl_0|dffs[21]~1435 at LC6
B1L44_p2_out = !Reset & B1_dffs[20] & B1_dffs[19] & B1_dffs[18] & B1_dffs[17] & B1_dffs[16] & B1_dffs[15] & B1_dffs[14] & B1_dffs[13] & B1_dffs[12] & B1_dffs[11] & B1_dffs[10] & B1_dffs[9] & B1_dffs[8] & B1_dffs[7] & B1_dffs[6] & B1_dffs[5] & B1_dffs[4] & B1_dffs[3] & B1_dffs[2] & B1_dffs[0] & B1_dffs[1];
B1L44_p3_out = Reset & B1_dffs[21];
B1L44_or_out = B1L44_p2_out # B1L44_p3_out;
B1L44 = B1_dffs[21] $ B1L44_or_out;


--B1_dffs[21] is lpm_counter:step_counter_rtl_0|dffs[21] at LC53
B1_dffs[21]_p2_out = !Reset & A1L7 & !A1L01 & !A1L11 & !A1L21 & !A1L31 & !A1L41 & !A1L51 & !A1L61 & !A1L71 & !A1L81 & !A1L91 & !A1L02 & !A1L12 & !A1L22 & !A1L32 & !A1L42 & !A1L52 & B1_dffs[21] & !B1L44 & A1L6 & A1L8 & A1L9;
B1_dffs[21]_p3_out = !Reset & A1L7 & !A1L01 & !A1L11 & !A1L21 & !A1L31 & !A1L41 & !A1L51 & !A1L61 & !A1L71 & !A1L81 & !A1L91 & !A1L02 & !A1L12 & !A1L22 & !A1L32 & !A1L42 & !A1L52 & !B1_dffs[21] & B1L44 & A1L6 & A1L8 & A1L9;
B1_dffs[21]_or_out = B1_dffs[21]_p2_out # B1_dffs[21]_p3_out;
B1_dffs[21]_reg_input = B1L44 $ B1_dffs[21]_or_out;
B1_dffs[21] = DFFE(B1_dffs[21]_reg_input, GLOBAL(pulse_sum_in), , , );


--B1L64 is lpm_counter:step_counter_rtl_0|dffs[22]~1445 at LC4
B1L64_p2_out = !Reset & B1_dffs[21] & B1_dffs[20] & B1_dffs[19] & B1_dffs[18] & B1_dffs[17] & B1_dffs[16] & B1_dffs[15] & B1_dffs[14] & B1_dffs[13] & B1_dffs[12] & B1_dffs[11] & B1_dffs[10] & B1_dffs[9] & B1_dffs[8] & B1_dffs[7] & B1_dffs[6] & B1_dffs[5] & B1_dffs[4] & B1_dffs[3] & B1_dffs[2] & B1_dffs[0] & B1_dffs[1];
B1L64_p3_out = Reset & B1_dffs[22];
B1L64_or_out = B1L64_p2_out # B1L64_p3_out;
B1L64 = B1_dffs[22] $ B1L64_or_out;


--B1_dffs[22] is lpm_counter:step_counter_rtl_0|dffs[22] at LC22
B1_dffs[22]_p2_out = !Reset & A1L7 & !A1L01 & !A1L11 & !A1L21 & !A1L31 & !A1L41 & !A1L51 & !A1L61 & !A1L71 & !A1L81 & !A1L91 & !A1L02 & !A1L12 & !A1L22 & !A1L32 & !A1L42 & !A1L52 & B1_dffs[22] & !B1L64 & A1L6 & A1L8 & A1L9;
B1_dffs[22]_p3_out = !Reset & A1L7 & !A1L01 & !A1L11 & !A1L21 & !A1L31 & !A1L41 & !A1L51 & !A1L61 & !A1L71 & !A1L81 & !A1L91 & !A1L02 & !A1L12 & !A1L22 & !A1L32 & !A1L42 & !A1L52 & !B1_dffs[22] & B1L64 & A1L6 & A1L8 & A1L9;
B1_dffs[22]_or_out = B1_dffs[22]_p2_out # B1_dffs[22]_p3_out;
B1_dffs[22]_reg_input = B1L64 $ B1_dffs[22]_or_out;
B1_dffs[22] = DFFE(B1_dffs[22]_reg_input, GLOBAL(pulse_sum_in), , , );


--B1L84 is lpm_counter:step_counter_rtl_0|dffs[23]~1455 at LC3
B1L84_p2_out = !Reset & B1_dffs[22] & B1_dffs[21] & B1_dffs[20] & B1_dffs[19] & B1_dffs[18] & B1_dffs[17] & B1_dffs[16] & B1_dffs[15] & B1_dffs[14] & B1_dffs[13] & B1_dffs[12] & B1_dffs[11] & B1_dffs[10] & B1_dffs[9] & B1_dffs[8] & B1_dffs[7] & B1_dffs[6] & B1_dffs[5] & B1_dffs[4] & B1_dffs[3] & B1_dffs[2] & B1_dffs[0] & B1_dffs[1];
B1L84_p3_out = Reset & B1_dffs[23];
B1L84_or_out = B1L84_p2_out # B1L84_p3_out;
B1L84 = B1_dffs[23] $ B1L84_or_out;


--B1_dffs[23] is lpm_counter:step_counter_rtl_0|dffs[23] at LC45
B1_dffs[23]_p2_out = !Reset & A1L7 & !A1L01 & !A1L11 & !A1L21 & !A1L31 & !A1L41 & !A1L51 & !A1L61 & !A1L71 & !A1L81 & !A1L91 & !A1L02 & !A1L12 & !A1L22 & !A1L32 & !A1L42 & !A1L52 & B1_dffs[23] & !B1L84 & A1L6 & A1L8 & A1L9;
B1_dffs[23]_p3_out = !Reset & A1L7 & !A1L01 & !A1L11 & !A1L21 & !A1L31 & !A1L41 & !A1L51 & !A1L61 & !A1L71 & !A1L81 & !A1L91 & !A1L02 & !A1L12 & !A1L22 & !A1L32 & !A1L42 & !A1L52 & !B1_dffs[23] & B1L84 & A1L6 & A1L8 & A1L9;
B1_dffs[23]_or_out = B1_dffs[23]_p2_out # B1_dffs[23]_p3_out;
B1_dffs[23]_reg_input = B1L84 $ B1_dffs[23]_or_out;
B1_dffs[23] = DFFE(B1_dffs[23]_reg_input, GLOBAL(pulse_sum_in), , , );


--A1L72 is out_control~62 at LC5
A1L72_p1_out = !out_control & B1_dffs[23] & B1_dffs[22] & B1_dffs[21] & B1_dffs[20] & B1_dffs[19] & B1_dffs[18] & B1_dffs[17] & B1_dffs[16] & B1_dffs[15] & B1_dffs[14] & B1_dffs[13] & B1_dffs[12] & B1_dffs[11] & B1_dffs[10] & B1_dffs[9] & B1_dffs[8] & B1_dffs[7] & B1_dffs[6] & B1_dffs[5] & B1_dffs[4] & B1_dffs[3] & B1_dffs[2] & B1_dffs[0] & B1_dffs[1];
A1L72_or_out = A1L72_p1_out;
A1L72 = A1L72_or_out;


--out_control is out_control at LC19
out_control_or_out = Reset # A1L82;
out_control_reg_input = !(out_control_or_out);
out_control = DFFE(out_control_reg_input, GLOBAL(pulse_sum_in), , , );


--A1L65 is wave_out~9 at LC97
A1L65_p1_out = out_control & pulse_sum_in;
A1L65_or_out = A1L65_p1_out;
A1L65 = A1L65_or_out;


--A1L9 is always0~229sexppiapart at LC110
A1L9_p1_out = B1_dffs[6] & !step_sum[6];
A1L9_p2_out = !B1_dffs[6] & step_sum[6];
A1L9_p3_out = B1_dffs[7] & !step_sum[7];
A1L9_p4_out = !B1_dffs[7] & step_sum[7];
A1L9_or_out = A1L9_p1_out # A1L9_p2_out # A1L9_p3_out # A1L9_p4_out;
A1L9 = !(A1L9_or_out);