📄 main.tan.qmsg
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{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst4\|pulse_1\[11\] " "Info: Node \"pulse_sum:inst4\|pulse_1\[11\]\"" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } } 0} } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Reset " "Info: Assuming node \"Reset\" is an undefined clock" { } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/main.bdf" { { 112 -200 -32 128 "Reset" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "Reset" } } } } } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "Clock_8MHz " "Info: Assuming node \"Clock_8MHz\" is an undefined clock" { } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/main.bdf" { { 248 -200 -32 264 "Clock_8MHz" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "Clock_8MHz" } } } } } 0} } { } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "71 " "Warning: Found 71 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~23 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~23\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~23" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "second_pulse_latch:inst3\|second_pulse_out\[11\] " "Info: Detected ripple clock \"second_pulse_latch:inst3\|second_pulse_out\[11\]\" as buffer" { } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/second_pulse_latch.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "second_pulse_latch:inst3\|second_pulse_out\[11\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~25 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~25\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~25" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "second_pulse_latch:inst3\|second_pulse_out\[12\] " "Info: Detected ripple clock \"second_pulse_latch:inst3\|second_pulse_out\[12\]\" as buffer" { } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/second_pulse_latch.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "second_pulse_latch:inst3\|second_pulse_out\[12\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~27 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~27\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~27" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "second_pulse_latch:inst3\|second_pulse_out\[13\] " "Info: Detected ripple clock \"second_pulse_latch:inst3\|second_pulse_out\[13\]\" as buffer" { } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/second_pulse_latch.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "second_pulse_latch:inst3\|second_pulse_out\[13\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~425 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~425\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~425" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "second_pulse_latch:inst3\|second_pulse_out\[14\] " "Info: Detected ripple clock \"second_pulse_latch:inst3\|second_pulse_out\[14\]\" as buffer" { } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/second_pulse_latch.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "second_pulse_latch:inst3\|second_pulse_out\[14\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~15 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~15\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~15" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "second_pulse_latch:inst3\|second_pulse_out\[7\] " "Info: Detected ripple clock \"second_pulse_latch:inst3\|second_pulse_out\[7\]\" as buffer" { } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/second_pulse_latch.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "second_pulse_latch:inst3\|second_pulse_out\[7\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~17 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~17\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~17" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "second_pulse_latch:inst3\|second_pulse_out\[8\] " "Info: Detected ripple clock \"second_pulse_latch:inst3\|second_pulse_out\[8\]\" as buffer" { } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/second_pulse_latch.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "second_pulse_latch:inst3\|second_pulse_out\[8\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~19 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~19\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~19" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "second_pulse_latch:inst3\|second_pulse_out\[9\] " "Info: Detected ripple clock \"second_pulse_latch:inst3\|second_pulse_out\[9\]\" as buffer" { } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/second_pulse_latch.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "second_pulse_latch:inst3\|second_pulse_out\[9\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~21 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~21\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~21" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "second_pulse_latch:inst3\|second_pulse_out\[10\] " "Info: Detected ripple clock \"second_pulse_latch:inst3\|second_pulse_out\[10\]\" as buffer" { } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/second_pulse_latch.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "second_pulse_latch:inst3\|second_pulse_out\[10\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1\[10\] " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1\[10\]\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[10\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1\[9\] " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1\[9\]\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[9\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1\[8\] " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1\[8\]\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[8\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1\[7\] " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1\[7\]\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[7\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~1 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~1\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~1" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[15\] " "Info: Detected ripple clock \"counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[15\]\" as buffer" { } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[15\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "second_pulse_latch:inst3\|second_pulse_out\[0\] " "Info: Detected ripple clock \"second_pulse_latch:inst3\|second_pulse_out\[0\]\" as buffer" { } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/second_pulse_latch.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "second_pulse_latch:inst3\|second_pulse_out\[0\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~3 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~3\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~3" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[14\] " "Info: Detected ripple clock \"counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[14\]\" as buffer" { } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[14\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "second_pulse_latch:inst3\|second_pulse_out\[1\] " "Info: Detected ripple clock \"second_pulse_latch:inst3\|second_pulse_out\[1\]\" as buffer" { } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/second_pulse_latch.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "second_pulse_latch:inst3\|second_pulse_out\[1\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~424 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~424\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~424" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~5 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~5\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~5" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[13\] " "Info: Detected ripple clock \"counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[13\]\" as buffer" { } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[13\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "second_pulse_latch:inst3\|second_pulse_out\[2\] " "Info: Detected ripple clock \"second_pulse_latch:inst3\|second_pulse_out\[2\]\" as buffer" { } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/second_pulse_latch.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "second_pulse_latch:inst3\|second_pulse_out\[2\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~7 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~7\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~7" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[12\] " "Info: Detected ripple clock \"counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[12\]\" as buffer" { } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[12\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "second_pulse_latch:inst3\|second_pulse_out\[3\] " "Info: Detected ripple clock \"second_pulse_latch:inst3\|second_pulse_out\[3\]\" as buffer" { } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/second_pulse_latch.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "second_pulse_latch:inst3\|second_pulse_out\[3\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~423 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~423\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~423" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~9 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~9\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~9" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[11\] " "Info: Detected ripple clock \"counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[11\]\" as buffer" { } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[11\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "second_pulse_latch:inst3\|second_pulse_out\[4\] " "Info: Detected ripple clock \"second_pulse_latch:inst3\|second_pulse_out\[4\]\" as buffer" { } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/second_pulse_latch.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "second_pulse_latch:inst3\|second_pulse_out\[4\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~11 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~11\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~11" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[10\] " "Info: Detected ripple clock \"counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[10\]\" as buffer" { } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[10\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "second_pulse_latch:inst3\|second_pulse_out\[5\] " "Info: Detected ripple clock \"second_pulse_latch:inst3\|second_pulse_out\[5\]\" as buffer" { } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/second_pulse_latch.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "second_pulse_latch:inst3\|second_pulse_out\[5\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~422 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~422\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~422" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~13 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~13\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~13" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[8\] " "Info: Detected ripple clock \"counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[8\]\" as buffer" { } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[8\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[9\] " "Info: Detected ripple clock \"counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[9\]\" as buffer" { } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[9\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\] " "Info: Detected ripple clock \"fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\]\" as buffer" { } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "second_pulse_latch:inst3\|second_pulse_out\[6\] " "Info: Detected ripple clock \"second_pulse_latch:inst3\|second_pulse_out\[6\]\" as buffer" { } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/second_pulse_latch.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "second_pulse_latch:inst3\|second_pulse_out\[6\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~421 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~421\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~421" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[7\] " "Info: Detected ripple clock \"counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[7\]\" as buffer" { } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[7\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[6\] " "Info: Detected ripple clock \"counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[6\]\" as buffer" { } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[6\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~420 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~420\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~420" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[5\] " "Info: Detected ripple clock \"counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[5\]\" as buffer" { } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[5\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[4\] " "Info: Detected ripple clock \"counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[4\]\" as buffer" { } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[4\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~419 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~419\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~419" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[3\] " "Info: Detected ripple clock \"counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[3\]\" as buffer" { } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[3\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[2\] " "Info: Detected ripple clock \"counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[2\]\" as buffer" { } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[2\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~418 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~418\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~418" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[1\] " "Info: Detected ripple clock \"counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[1\]\" as buffer" { } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[1\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[0\] " "Info: Detected ripple clock \"counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[0\]\" as buffer" { } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[0\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\] " "Info: Detected ripple clock \"fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\]\" as buffer" { } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1\[14\] " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1\[14\]\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[14\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1\[13\] " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1\[13\]\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[13\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1\[12\] " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1\[12\]\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[12\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1\[11\] " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1\[11\]\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[11\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1\[2\] " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1\[2\]\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[2\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1\[1\] " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1\[1\]\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[1\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1\[0\] " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1\[0\]\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[0\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1\[6\] " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1\[6\]\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[6\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1\[5\] " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1\[5\]\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[5\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1\[4\] " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1\[4\]\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[4\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1\[3\] " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1\[3\]\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[3\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_out~16 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_out~16\" as buffer" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_out~16" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Reset register sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] register sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[23\] 87.72 MHz 11.4 ns Internal " "Info: Clock \"Reset\" has Internal fmax of 87.72 MHz between source register \"sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]\" and destination register \"sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[23\]\" (period= 11.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.400 ns + Longest register register " "Info: + Longest register to register delay is 6.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 1 REG LC4_B3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_B3; Fanout = 4; REG Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.700 ns) 1.300 ns sum_control:inst5\|reduce_nor~288 2 COMB LC5_B2 1 " "Info: 2: + IC(0.600 ns) + CELL(0.700 ns) = 1.300 ns; Loc. = LC5_B2; Fanout = 1; COMB Node = 'sum_control:inst5\|reduce_nor~288'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.300 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] sum_control:inst5|reduce_nor~288 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 2.300 ns sum_control:inst5\|reduce_nor~297 3 COMB LC6_B2 1 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 2.300 ns; Loc. = LC6_B2; Fanout = 1; COMB Node = 'sum_control:inst5\|reduce_nor~297'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.000 ns" { sum_control:inst5|reduce_nor~288 sum_control:inst5|reduce_nor~297 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.100 ns) 4.000 ns sum_control:inst5\|reduce_nor~267 4 COMB LC4_B6 2 " "Info: 4: + IC(0.600 ns) + CELL(1.100 ns) = 4.000 ns; Loc. = LC4_B6; Fanout = 2; COMB Node = 'sum_control:inst5\|reduce_nor~267'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.700 ns" { sum_control:inst5|reduce_nor~297 sum_control:inst5|reduce_nor~267 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.000 ns) 5.100 ns rtl~0 5 COMB LC1_B6 54 " "Info: 5: + IC(0.100 ns) + CELL(1.000 ns) = 5.100 ns; Loc. = LC1_B6; Fanout = 54; COMB Node = 'rtl~0'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.100 ns" { sum_control:inst5|reduce_nor~267 rtl~0 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.700 ns) 6.400 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[23\] 6 REG LC8_B7 3 " "Info: 6: + IC(0.600 ns) + CELL(0.700 ns) = 6.400 ns; Loc. = LC8_B7; Fanout = 3; REG Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[23\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.300 ns" { rtl~0 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns 70.31 % " "Info: Total cell delay = 4.500 ns ( 70.31 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.900 ns 29.69 % " "Info: Total interconnect delay = 1.900 ns ( 29.69 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "6.400 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] sum_control:inst5|reduce_nor~288 sum_control:inst5|reduce_nor~297 sum_control:inst5|reduce_nor~267 rtl~0 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.400 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] sum_control:inst5|reduce_nor~288 sum_control:inst5|reduce_nor~297 sum_control:inst5|reduce_nor~267 rtl~0 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] } { 0.000ns 0.600ns 0.000ns 0.600ns 0.100ns 0.600ns } { 0.000ns 0.700ns 1.000ns 1.100ns 1.000ns 0.700ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.300 ns - Smallest " "Info: - Smallest clock skew is -4.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Reset destination 4.500 ns + Shortest register " "Info: + Shortest clock path from clock \"Reset\" to destination register is 4.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Reset 1 CLK PIN_89 51 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_89; Fanout = 51; CLK Node = 'Reset'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { Reset } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/main.bdf" { { 112 -200 -32 128 "Reset" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.000 ns) 2.400 ns pulse_sum:inst4\|pulse_out~16 2 COMB LC1_A10 28 " "Info: 2: + IC(0.100 ns) + CELL(1.000 ns) = 2.400 ns; Loc. = LC1_A10; Fanout = 28; COMB Node = 'pulse_sum:inst4\|pulse_out~16'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.100 ns" { Reset pulse_sum:inst4|pulse_out~16 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(0.000 ns) 4.500 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[23\] 3 REG LC8_B7 3 " "Info: 3: + IC(2.100 ns) + CELL(0.000 ns) = 4.500 ns; Loc. = LC8_B7; Fanout = 3; REG Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[23\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "2.100 ns" { pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.300 ns 51.11 % " "Info: Total cell delay = 2.300 ns ( 51.11 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.200 ns 48.89 % " "Info: Total interconnect delay = 2.200 ns ( 48.89 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "4.500 ns" { Reset pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.500 ns" { Reset Reset~out pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] } { 0.000ns 0.000ns 0.100ns 2.100ns } { 0.000ns 1.300ns 1.000ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Reset source 8.800 ns - Longest register " "Info: - Longest clock path from clock \"Reset\" to source register is 8.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Reset 1 CLK PIN_89 51 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_89; Fanout = 51; CLK Node = 'Reset'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { Reset } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/main.bdf" { { 112 -200 -32 128 "Reset" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 2.300 ns pulse_sum:inst4\|pulse_1\[5\] 2 COMB LOOP LC8_A9 2 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 2.300 ns; Loc. = LC8_A9; Fanout = 2; COMB LOOP Node = 'pulse_sum:inst4\|pulse_1\[5\]'" { { "Info" "ITDB_PART_OF_SCC" "pulse_sum:inst4\|pulse_1\[5\] LC8_A9 " "Info: Loc. = LC8_A9; Node \"pulse_sum:inst4\|pulse_1\[5\]\"" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { pulse_sum:inst4|pulse_1[5] } "NODE_NAME" } "" } } } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { pulse_sum:inst4|pulse_1[5] } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.000 ns" { Reset pulse_sum:inst4|pulse_1[5] } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(1.000 ns) 4.000 ns pulse_sum:inst4\|pulse_out~126 3 COMB LC3_A1 1 " "Info: 3: + IC(0.700 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC3_A1; Fanout = 1; COMB Node = 'pulse_sum:inst4\|pulse_out~126'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.700 ns" { pulse_sum:inst4|pulse_1[5] pulse_sum:inst4|pulse_out~126 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.800 ns) 5.800 ns pulse_sum:inst4\|pulse_out~127 4 COMB LC2_A10 2 " "Info: 4: + IC(1.000 ns) + CELL(0.800 ns) = 5.800 ns; Loc. = LC2_A10; Fanout = 2; COMB Node = 'pulse_sum:inst4\|pulse_out~127'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.800 ns" { pulse_sum:inst4|pulse_out~126 pulse_sum:inst4|pulse_out~127 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.800 ns) 6.700 ns pulse_sum:inst4\|pulse_out~16 5 COMB LC1_A10 28 " "Info: 5: + IC(0.100 ns) + CELL(0.800 ns) = 6.700 ns; Loc. = LC1_A10; Fanout = 28; COMB Node = 'pulse_sum:inst4\|pulse_out~16'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.900 ns" { pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(0.000 ns) 8.800 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 6 REG LC4_B3 4 " "Info: 6: + IC(2.100 ns) + CELL(0.000 ns) = 8.800 ns; Loc. = LC4_B3; Fanout = 4; REG Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "2.100 ns" { pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.900 ns 55.68 % " "Info: Total cell delay = 4.900 ns ( 55.68 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.900 ns 44.32 % " "Info: Total interconnect delay = 3.900 ns ( 44.32 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "8.800 ns" { Reset pulse_sum:inst4|pulse_1[5] pulse_sum:inst4|pulse_out~126 pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.800 ns" { Reset Reset~out pulse_sum:inst4|pulse_1[5] pulse_sum:inst4|pulse_out~126 pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 0.000ns 0.700ns 1.000ns 0.100ns 2.100ns } { 0.000ns 1.300ns 1.000ns 1.000ns 0.800ns 0.800ns 0.000ns } } } } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "4.500 ns" { Reset pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.500 ns" { Reset Reset~out pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0⌨️ 快捷键说明
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