main.tan.rpt
来自「步进电机位置控制系统的FPGA设计与实现。」· RPT 代码 · 共 246 行 · 第 1/5 页
RPT
246 行
; N/A ; 90.09 MHz ( period = 11.100 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; Reset ; Reset ; None ; None ; 6.100 ns ;
; N/A ; 90.09 MHz ( period = 11.100 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; Reset ; Reset ; None ; None ; 6.100 ns ;
; N/A ; 90.09 MHz ( period = 11.100 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; Reset ; Reset ; None ; None ; 6.100 ns ;
; N/A ; 90.09 MHz ( period = 11.100 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6] ; Reset ; Reset ; None ; None ; 6.100 ns ;
; N/A ; 90.09 MHz ( period = 11.100 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6] ; Reset ; Reset ; None ; None ; 6.100 ns ;
; N/A ; 90.09 MHz ( period = 11.100 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6] ; Reset ; Reset ; None ; None ; 6.100 ns ;
; N/A ; 90.09 MHz ( period = 11.100 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7] ; Reset ; Reset ; None ; None ; 6.100 ns ;
; N/A ; 90.09 MHz ( period = 11.100 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7] ; Reset ; Reset ; None ; None ; 6.100 ns ;
; N/A ; 90.09 MHz ( period = 11.100 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7] ; Reset ; Reset ; None ; None ; 6.100 ns ;
; N/A ; 90.09 MHz ( period = 11.100 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8] ; Reset ; Reset ; None ; None ; 6.100 ns ;
; N/A ; 90.09 MHz ( period = 11.100 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8] ; Reset ; Reset ; None ; None ; 6.100 ns ;
; N/A ; 90.09 MHz ( period = 11.100 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8] ; Reset ; Reset ; None ; None ; 6.100 ns ;
; N/A ; 90.91 MHz ( period = 11.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset ; Reset ; None ; None ; 6.000 ns ;
; N/A ; 90.91 MHz ( period = 11.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset ; Reset ; None ; None ; 6.000 ns ;
; N/A ; 90.91 MHz ( period = 11.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Reset ; Reset ; None ; None ; 6.000 ns ;
; N/A ; 90.91 MHz ( period = 11.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Reset ; Reset ; None ; None ; 6.000 ns ;
; N/A ; 90.91 MHz ( period = 11.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Reset ; Reset ; None ; None ; 6.000 ns ;
; N/A ; 90.91 MHz ( period = 11.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Reset ; Reset ; None ; None ; 6.000 ns ;
; N/A ; 90.91 MHz ( period = 11.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Reset ; Reset ; None ; None ; 6.000 ns ;
; N/A ; 90.91 MHz ( period = 11.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Reset ; Reset ; None ; None ; 6.000 ns ;
; N/A ; 90.91 MHz ( period = 11.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Reset ; Reset ; None ; None ; 6.000 ns ;
; N/A ; 90.91 MHz ( period = 11.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Reset ; Reset ; None ; None ; 6.000 ns ;
; N/A ; 90.91 MHz ( period = 11.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Reset ; Reset ; None ; None ; 6.000 ns ;
; N/A ; 90.91 MHz ( period = 11.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Reset ; Reset ; None ; None ; 6.000 ns ;
; N/A ; 90.91 MHz ( period = 11.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset ; Reset ; None ; None ; 6.000 ns ;
; N/A ; 90.91 MHz ( period = 11.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset ; Reset ; None ; None ; 6.000 ns ;
; N/A ; 90.91 MHz ( period = 11.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9] ; Reset ; Reset ; None ; None ; 6.000 ns ;
; N/A ; 90.91 MHz ( period = 11.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Reset ; Reset ; None ; None ; 6.000 ns ;
; N/A ; 90.91 MHz ( period = 11.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Reset ; Reset ; None ; None ; 6.000 ns ;
; N/A ; 90.91 MHz ( period = 11.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Reset ; Reset ; None ; None ; 6.000 ns ;
; N/A ; 90.91 MHz ( period = 11.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Reset ; Reset ; None ; None ; 6.000 ns ;
; N/A ; 90.91 MHz ( period = 11.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Reset ; Reset ; None ; None ; 6.000 ns ;
; N/A ; 90.91 MHz ( period = 11.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Reset ; Reset ; None ; None ; 6.000 ns ;
; N/A ; 90.91 MHz ( period = 11.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset ; Reset ; None ; None ; 6.000 ns ;
; N/A ; 90.91 MHz ( period = 11.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset ; Reset ; None ; None ; 6.000 ns ;
; N/A ; 90.91 MHz ( period = 11.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; Reset ; Reset ; None ; None ; 6.000 ns ;
; N/A ; 90.91 MHz ( period = 11.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; Reset ; Reset ; None ; None ; 6.000 ns ;
; N/A ; 90.91 MHz ( period = 11.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; Reset ; Reset ; None ; None ; 6.000 ns ;
; N/A ; 90.91 MHz ( period = 11.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; Reset ; Reset ; None ; None ; 6.000 ns ;
; N/A ; 90.91 MHz ( period = 11.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; Reset ; Reset ; None ; None ; 6.000 ns ;
; N/A ; 90.91 MHz ( period = 11.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; Reset ; Reset ; None ; None ; 6.000 ns ;
; N/A ; 90.91 MHz ( period = 11.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6] ; Reset ; Reset ; None ; None ; 6.000 ns ;
; N/A ; 90.91 MHz ( period = 11.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7] ; Reset ; Reset ; None ; None ; 6.000 ns ;
; N/A ; 90.91 MHz ( period = 11.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8] ; Reset ; Reset ; None ; None ; 6.000 ns ;
; N/A ; 91.74 MHz ( period = 10.900 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset ; Reset ; None ; None ; 5.900 ns ;
; N/A ; 91.74 MHz ( period = 10.900 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_c⌨️ 快捷键说明
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