trafficlight.tan.qmsg

交通灯控制系统的FPGA设计与实现

{ "Info" "ITDB_TH_RESULT" "counter05:inst1\|C_out Reset CLK 3.717 ns register " "Info: th for register \"counter05:inst1\|C_out\" (data pin = \"Reset\", clock pin = \"CLK\") is 3.717 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 9.594 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 9.594 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLK 1 CLK PIN_10 33 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 33; CLK Node = 'CLK'" {  } { { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "" { CLK } "NODE_NAME" } "" } } { "trafficlight.bdf" "" { Schematic "F:/dolphin/trafficlight/trafficlight.bdf" { { 776 240 408 792 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.720 ns) 2.301 ns fdiv1khz:inst12\|clk_out 2 REG LC_X7_Y10_N6 34 " "Info: 2: + IC(0.451 ns) + CELL(0.720 ns) = 2.301 ns; Loc. = LC_X7_Y10_N6; Fanout = 34; REG Node = 'fdiv1khz:inst12\|clk_out'" {  } { { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "1.171 ns" { CLK fdiv1khz:inst12|clk_out } "NODE_NAME" } "" } } { "fdiv1khz.v" "" { Text "F:/dolphin/trafficlight/fdiv1khz.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.050 ns) + CELL(0.720 ns) 6.071 ns fdiv1hz:inst11\|clk_out 3 REG LC_X10_Y6_N6 14 " "Info: 3: + IC(3.050 ns) + CELL(0.720 ns) = 6.071 ns; Loc. = LC_X10_Y6_N6; Fanout = 14; REG Node = 'fdiv1hz:inst11\|clk_out'" {  } { { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "3.770 ns" { fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out } "NODE_NAME" } "" } } { "fdiv1hz.v" "" { Text "F:/dolphin/trafficlight/fdiv1hz.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.976 ns) + CELL(0.547 ns) 9.594 ns counter05:inst1\|C_out 4 REG LC_X19_Y6_N7 1 " "Info: 4: + IC(2.976 ns) + CELL(0.547 ns) = 9.594 ns; Loc. = LC_X19_Y6_N7; Fanout = 1; REG Node = 'counter05:inst1\|C_out'" {  } { { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "3.523 ns" { fdiv1hz:inst11|clk_out counter05:inst1|C_out } "NODE_NAME" } "" } } { "counter05.v" "" { Text "F:/dolphin/trafficlight/counter05.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.117 ns 32.49 % " "Info: Total cell delay = 3.117 ns ( 32.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.477 ns 67.51 % " "Info: Total interconnect delay = 6.477 ns ( 67.51 % )" {  } {  } 0}  } { { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "9.594 ns" { CLK fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter05:inst1|C_out } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "9.594 ns" { CLK CLK~out0 fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter05:inst1|C_out } { 0.000ns 0.000ns 0.451ns 3.050ns 2.976ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.012 ns + " "Info: + Micro hold delay of destination is 0.012 ns" {  } { { "counter05.v" "" { Text "F:/dolphin/trafficlight/counter05.v" 4 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.889 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.889 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns Reset 1 PIN PIN_84 11 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_84; Fanout = 11; PIN Node = 'Reset'" {  } { { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "" { Reset } "NODE_NAME" } "" } } { "trafficlight.bdf" "" { Schematic "F:/dolphin/trafficlight/trafficlight.bdf" { { 728 240 408 744 "Reset" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.386 ns) + CELL(0.368 ns) 5.889 ns counter05:inst1\|C_out 2 REG LC_X19_Y6_N7 1 " "Info: 2: + IC(4.386 ns) + CELL(0.368 ns) = 5.889 ns; Loc. = LC_X19_Y6_N7; Fanout = 1; REG Node = 'counter05:inst1\|C_out'" {  } { { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "4.754 ns" { Reset counter05:inst1|C_out } "NODE_NAME" } "" } } { "counter05.v" "" { Text "F:/dolphin/trafficlight/counter05.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.503 ns 25.52 % " "Info: Total cell delay = 1.503 ns ( 25.52 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.386 ns 74.48 % " "Info: Total interconnect delay = 4.386 ns ( 74.48 % )" {  } {  } 0}  } { { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "5.889 ns" { Reset counter05:inst1|C_out } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "5.889 ns" { Reset Reset~out0 counter05:inst1|C_out } { 0.000ns 0.000ns 4.386ns } { 0.000ns 1.135ns 0.368ns } } }  } 0}  } { { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "9.594 ns" { CLK fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter05:inst1|C_out } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "9.594 ns" { CLK CLK~out0 fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter05:inst1|C_out } { 0.000ns 0.000ns 0.451ns 3.050ns 2.976ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.547ns } } } { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "5.889 ns" { Reset counter05:inst1|C_out } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "5.889 ns" { Reset Reset~out0 counter05:inst1|C_out } { 0.000ns 0.000ns 4.386ns } { 0.000ns 1.135ns 0.368ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun May 28 11:10:22 2006 " "Info: Processing ended: Sun May 28 11:10:22 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}