trafficlight.tan.qmsg

交通灯控制系统的FPGA设计与实现

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "trafficlight.bdf" "" { Schematic "F:/dolphin/trafficlight/trafficlight.bdf" { { 776 240 408 792 "CLK" "" } } } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "5 " "Warning: Found 5 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "fdiv1hz:inst11\|clk_out " "Info: Detected ripple clock \"fdiv1hz:inst11\|clk_out\" as buffer" {  } { { "fdiv1hz.v" "" { Text "F:/dolphin/trafficlight/fdiv1hz.v" 3 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "fdiv1hz:inst11\|clk_out" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "fdiv1khz:inst12\|clk_out " "Info: Detected ripple clock \"fdiv1khz:inst12\|clk_out\" as buffer" {  } { { "fdiv1khz.v" "" { Text "F:/dolphin/trafficlight/fdiv1khz.v" 3 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "fdiv1khz:inst12\|clk_out" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "counter55:inst2\|C_out " "Info: Detected ripple clock \"counter55:inst2\|C_out\" as buffer" {  } { { "counter55.v" "" { Text "F:/dolphin/trafficlight/counter55.v" 4 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter55:inst2\|C_out" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "counter05:inst1\|C_out " "Info: Detected ripple clock \"counter05:inst1\|C_out\" as buffer" {  } { { "counter05.v" "" { Text "F:/dolphin/trafficlight/counter05.v" 4 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter05:inst1\|C_out" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "scan:inst\|EN_in " "Info: Detected gated clock \"scan:inst\|EN_in\" as buffer" {  } { { "scan.v" "" { Text "F:/dolphin/trafficlight/scan.v" 9 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "scan:inst\|EN_in" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register scan:inst\|sdata\[0\] register counter55:inst2\|lpm_counter:CData0_rtl_0\|cntr_0b7:auto_generated\|safe_q\[2\] 131.37 MHz 7.612 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 131.37 MHz between source register \"scan:inst\|sdata\[0\]\" and destination register \"counter55:inst2\|lpm_counter:CData0_rtl_0\|cntr_0b7:auto_generated\|safe_q\[2\]\" (period= 7.612 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.754 ns + Longest register register " "Info: + Longest register to register delay is 2.754 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns scan:inst\|sdata\[0\] 1 REG LC_X19_Y6_N3 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y6_N3; Fanout = 19; REG Node = 'scan:inst\|sdata\[0\]'" {  } { { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "" { scan:inst|sdata[0] } "NODE_NAME" } "" } } { "scan.v" "" { Text "F:/dolphin/trafficlight/scan.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.983 ns) + CELL(0.340 ns) 1.323 ns counter55:inst2\|CData0\[0\]~21 2 COMB LC_X19_Y8_N4 8 " "Info: 2: + IC(0.983 ns) + CELL(0.340 ns) = 1.323 ns; Loc. = LC_X19_Y8_N4; Fanout = 8; COMB Node = 'counter55:inst2\|CData0\[0\]~21'" {  } { { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "1.323 ns" { scan:inst|sdata[0] counter55:inst2|CData0[0]~21 } "NODE_NAME" } "" } } { "counter55.v" "" { Text "F:/dolphin/trafficlight/counter55.v" 53 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.575 ns) + CELL(0.856 ns) 2.754 ns counter55:inst2\|lpm_counter:CData0_rtl_0\|cntr_0b7:auto_generated\|safe_q\[2\] 3 REG LC_X20_Y8_N7 8 " "Info: 3: + IC(0.575 ns) + CELL(0.856 ns) = 2.754 ns; Loc. = LC_X20_Y8_N7; Fanout = 8; REG Node = 'counter55:inst2\|lpm_counter:CData0_rtl_0\|cntr_0b7:auto_generated\|safe_q\[2\]'" {  } { { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "1.431 ns" { counter55:inst2|CData0[0]~21 counter55:inst2|lpm_counter:CData0_rtl_0|cntr_0b7:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "db/cntr_0b7.tdf" "" { Text "F:/dolphin/trafficlight/db/cntr_0b7.tdf" 77 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.196 ns 43.43 % " "Info: Total cell delay = 1.196 ns ( 43.43 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.558 ns 56.57 % " "Info: Total interconnect delay = 1.558 ns ( 56.57 % )" {  } {  } 0}  } { { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "2.754 ns" { scan:inst|sdata[0] counter55:inst2|CData0[0]~21 counter55:inst2|lpm_counter:CData0_rtl_0|cntr_0b7:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.754 ns" { scan:inst|sdata[0] counter55:inst2|CData0[0]~21 counter55:inst2|lpm_counter:CData0_rtl_0|cntr_0b7:auto_generated|safe_q[2] } { 0.000ns 0.983ns 0.575ns } { 0.000ns 0.340ns 0.856ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.656 ns - Smallest " "Info: - Smallest clock skew is -4.656 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 9.594 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 9.594 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLK 1 CLK PIN_10 33 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 33; CLK Node = 'CLK'" {  } { { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "" { CLK } "NODE_NAME" } "" } } { "trafficlight.bdf" "" { Schematic "F:/dolphin/trafficlight/trafficlight.bdf" { { 776 240 408 792 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.720 ns) 2.301 ns fdiv1khz:inst12\|clk_out 2 REG LC_X7_Y10_N6 34 " "Info: 2: + IC(0.451 ns) + CELL(0.720 ns) = 2.301 ns; Loc. = LC_X7_Y10_N6; Fanout = 34; REG Node = 'fdiv1khz:inst12\|clk_out'" {  } { { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "1.171 ns" { CLK fdiv1khz:inst12|clk_out } "NODE_NAME" } "" } } { "fdiv1khz.v" "" { Text "F:/dolphin/trafficlight/fdiv1khz.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.050 ns) + CELL(0.720 ns) 6.071 ns fdiv1hz:inst11\|clk_out 3 REG LC_X10_Y6_N6 14 " "Info: 3: + IC(3.050 ns) + CELL(0.720 ns) = 6.071 ns; Loc. = LC_X10_Y6_N6; Fanout = 14; REG Node = 'fdiv1hz:inst11\|clk_out'" {  } { { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "3.770 ns" { fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out } "NODE_NAME" } "" } } { "fdiv1hz.v" "" { Text "F:/dolphin/trafficlight/fdiv1hz.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.976 ns) + CELL(0.547 ns) 9.594 ns counter55:inst2\|lpm_counter:CData0_rtl_0\|cntr_0b7:auto_generated\|safe_q\[2\] 4 REG LC_X20_Y8_N7 8 " "Info: 4: + IC(2.976 ns) + CELL(0.547 ns) = 9.594 ns; Loc. = LC_X20_Y8_N7; Fanout = 8; REG Node = 'counter55:inst2\|lpm_counter:CData0_rtl_0\|cntr_0b7:auto_generated\|safe_q\[2\]'" {  } { { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "3.523 ns" { fdiv1hz:inst11|clk_out counter55:inst2|lpm_counter:CData0_rtl_0|cntr_0b7:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "db/cntr_0b7.tdf" "" { Text "F:/dolphin/trafficlight/db/cntr_0b7.tdf" 77 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.117 ns 32.49 % " "Info: Total cell delay = 3.117 ns ( 32.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.477 ns 67.51 % " "Info: Total interconnect delay = 6.477 ns ( 67.51 % )" {  } {  } 0}  } { { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "9.594 ns" { CLK fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter55:inst2|lpm_counter:CData0_rtl_0|cntr_0b7:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "9.594 ns" { CLK CLK~out0 fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter55:inst2|lpm_counter:CData0_rtl_0|cntr_0b7:auto_generated|safe_q[2] } { 0.000ns 0.000ns 0.451ns 3.050ns 2.976ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 14.250 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 14.250 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLK 1 CLK PIN_10 33 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 33; CLK Node = 'CLK'" {  } { { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "" { CLK } "NODE_NAME" } "" } } { "trafficlight.bdf" "" { Schematic "F:/dolphin/trafficlight/trafficlight.bdf" { { 776 240 408 792 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.720 ns) 2.301 ns fdiv1khz:inst12\|clk_out 2 REG LC_X7_Y10_N6 34 " "Info: 2: + IC(0.451 ns) + CELL(0.720 ns) = 2.301 ns; Loc. = LC_X7_Y10_N6; Fanout = 34; REG Node = 'fdiv1khz:inst12\|clk_out'" {  } { { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "1.171 ns" { CLK fdiv1khz:inst12|clk_out } "NODE_NAME" } "" } } { "fdiv1khz.v" "" { Text "F:/dolphin/trafficlight/fdiv1khz.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.050 ns) + CELL(0.720 ns) 6.071 ns fdiv1hz:inst11\|clk_out 3 REG LC_X10_Y6_N6 14 " "Info: 3: + IC(3.050 ns) + CELL(0.720 ns) = 6.071 ns; Loc. = LC_X10_Y6_N6; Fanout = 14; REG Node = 'fdiv1hz:inst11\|clk_out'" {  } { { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "3.770 ns" { fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out } "NODE_NAME" } "" } } { "fdiv1hz.v" "" { Text "F:/dolphin/trafficlight/fdiv1hz.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.976 ns) + CELL(0.720 ns) 9.767 ns counter05:inst1\|C_out 4 REG LC_X19_Y6_N7 1 " "Info: 4: + IC(2.976 ns) + CELL(0.720 ns) = 9.767 ns; Loc. = LC_X19_Y6_N7; Fanout = 1; REG Node = 'counter05:inst1\|C_out'" {  } { { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "3.696 ns" { fdiv1hz:inst11|clk_out counter05:inst1|C_out } "NODE_NAME" } "" } } { "counter05.v" "" { Text "F:/dolphin/trafficlight/counter05.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.416 ns) + CELL(0.225 ns) 10.408 ns scan:inst\|EN_in 5 COMB LC_X19_Y6_N9 2 " "Info: 5: + IC(0.416 ns) + CELL(0.225 ns) = 10.408 ns; Loc. = LC_X19_Y6_N9; Fanout = 2; COMB Node = 'scan:inst\|EN_in'" {  } { { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "0.641 ns" { counter05:inst1|C_out scan:inst|EN_in } "NODE_NAME" } "" } } { "scan.v" "" { Text "F:/dolphin/trafficlight/scan.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.295 ns) + CELL(0.547 ns) 14.250 ns scan:inst\|sdata\[0\] 6 REG LC_X19_Y6_N3 19 " "Info: 6: + IC(3.295 ns) + CELL(0.547 ns) = 14.250 ns; Loc. = LC_X19_Y6_N3; Fanout = 19; REG Node = 'scan:inst\|sdata\[0\]'" {  } { { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "3.842 ns" { scan:inst|EN_in scan:inst|sdata[0] } "NODE_NAME" } "" } } { "scan.v" "" { Text "F:/dolphin/trafficlight/scan.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.062 ns 28.51 % " "Info: Total cell delay = 4.062 ns ( 28.51 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.188 ns 71.49 % " "Info: Total interconnect delay = 10.188 ns ( 71.49 % )" {  } {  } 0}  } { { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "14.250 ns" { CLK fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter05:inst1|C_out scan:inst|EN_in scan:inst|sdata[0] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "14.250 ns" { CLK CLK~out0 fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter05:inst1|C_out scan:inst|EN_in scan:inst|sdata[0] } { 0.000ns 0.000ns 0.451ns 3.050ns 2.976ns 0.416ns 3.295ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.720ns 0.225ns 0.547ns } } }  } 0}  } { { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "9.594 ns" { CLK fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter55:inst2|lpm_counter:CData0_rtl_0|cntr_0b7:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "9.594 ns" { CLK CLK~out0 fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter55:inst2|lpm_counter:CData0_rtl_0|cntr_0b7:auto_generated|safe_q[2] } { 0.000ns 0.000ns 0.451ns 3.050ns 2.976ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.547ns } } } { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "14.250 ns" { CLK fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter05:inst1|C_out scan:inst|EN_in scan:inst|sdata[0] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "14.250 ns" { CLK CLK~out0 fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter05:inst1|C_out scan:inst|EN_in scan:inst|sdata[0] } { 0.000ns 0.000ns 0.451ns 3.050ns 2.976ns 0.416ns 3.295ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.720ns 0.225ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "scan.v" "" { Text "F:/dolphin/trafficlight/scan.v" 4 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "db/cntr_0b7.tdf" "" { Text "F:/dolphin/trafficlight/db/cntr_0b7.tdf" 77 8 0 } }  } 0}  } { { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "2.754 ns" { scan:inst|sdata[0] counter55:inst2|CData0[0]~21 counter55:inst2|lpm_counter:CData0_rtl_0|cntr_0b7:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.754 ns" { scan:inst|sdata[0] counter55:inst2|CData0[0]~21 counter55:inst2|lpm_counter:CData0_rtl_0|cntr_0b7:auto_generated|safe_q[2] } { 0.000ns 0.983ns 0.575ns } { 0.000ns 0.340ns 0.856ns } } } { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "9.594 ns" { CLK fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter55:inst2|lpm_counter:CData0_rtl_0|cntr_0b7:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "9.594 ns" { CLK CLK~out0 fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter55:inst2|lpm_counter:CData0_rtl_0|cntr_0b7:auto_generated|safe_q[2] } { 0.000ns 0.000ns 0.451ns 3.050ns 2.976ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.547ns } } } { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "14.250 ns" { CLK fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter05:inst1|C_out scan:inst|EN_in scan:inst|sdata[0] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "14.250 ns" { CLK CLK~out0 fdiv1khz:inst12|clk_out fdiv1hz:inst11|clk_out counter05:inst1|C_out scan:inst|EN_in scan:inst|sdata[0] } { 0.000ns 0.000ns 0.451ns 3.050ns 2.976ns 0.416ns 3.295ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.720ns 0.225ns 0.547ns } } }  } 0}