trafficlight.tan.rpt

交通灯控制系统的FPGA设计与实现

; Worst-case tco               ; N/A   ; None          ; 23.122 ns                        ; scan:inst|sdata[0] ; SEG_Data[7]                                                                ; CLK        ;          ; 0            ;
; Worst-case tpd               ; N/A   ; None          ; 9.103 ns                         ; SW                 ; Green2                                                                     ;            ;          ; 0            ;
; Worst-case th                ; N/A   ; None          ; 3.717 ns                         ; Reset              ; counter05:inst1|C_out                                                      ;            ; CLK      ; 0            ;
; Clock Setup: 'CLK'           ; N/A   ; None          ; 131.37 MHz ( period = 7.612 ns ) ; scan:inst|sdata[0] ; counter55:inst2|lpm_counter:CData0_rtl_0|cntr_0b7:auto_generated|safe_q[0] ; CLK        ; CLK      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                    ;                                                                            ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+--------------------+----------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C3T100C6        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minumum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Clock Analysis Only                                   ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Do Min/Max analysis using Rise/Fall delays            ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Use Clock Latency for PLL offset                      ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; CLK             ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                                                                                                                                                ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------+----------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                     ; To                                                                         ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------+----------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 131.37 MHz ( period = 7.612 ns )                    ; scan:inst|sdata[0]                                                       ; counter55:inst2|lpm_counter:CData0_rtl_0|cntr_0b7:auto_generated|safe_q[2] ; CLK        ; CLK      ; None                        ; None                      ; 2.754 ns                ;
; N/A                                     ; 131.37 MHz ( period = 7.612 ns )                    ; scan:inst|sdata[0]                                                       ; counter55:inst2|lpm_counter:CData0_rtl_0|cntr_0b7:auto_generated|safe_q[1] ; CLK        ; CLK      ; None                        ; None                      ; 2.754 ns                ;
; N/A                                     ; 131.37 MHz ( period = 7.612 ns )                    ; scan:inst|sdata[0]                                                       ; counter55:inst2|lpm_counter:CData0_rtl_0|cntr_0b7:auto_generated|safe_q[3] ; CLK        ; CLK      ; None                        ; None                      ; 2.754 ns                ;