trafficlight.v

来自「交通灯控制系统的FPGA设计与实现」· Verilog 代码 · 共 83 行

module trafficlight(
	Reset,
	SW,
	CLK,
	Red1,
	Red2,
	Yellow1,
	Yellow2,
	Green1,
	Green2,
	SEG_Data,
	SEG_Sel
);

input	Reset;
input	SW;
input	CLK;
output	Red1;
output	Red2;
output	Yellow1;
output	Yellow2;
output	Green1;
output	Green2;
output	[7:0] SEG_Data;
output	[1:0] SEG_Sel;

wire	SYNTHESIZED_WIRE_0;
wire	SYNTHESIZED_WIRE_1;
wire	SYNTHESIZED_WIRE_19;
wire	SYNTHESIZED_WIRE_3;
wire	SYNTHESIZED_WIRE_20;
wire	[1:0] SYNTHESIZED_WIRE_21;
wire	SYNTHESIZED_WIRE_7;
wire	[3:0] SYNTHESIZED_WIRE_9;
wire	[3:0] SYNTHESIZED_WIRE_10;
wire	[3:0] SYNTHESIZED_WIRE_11;
wire	[3:0] SYNTHESIZED_WIRE_12;
wire	[3:0] SYNTHESIZED_WIRE_14;
wire	[3:0] SYNTHESIZED_WIRE_15;
wire	[3:0] SYNTHESIZED_WIRE_16;
wire	[1:0] SYNTHESIZED_WIRE_17;

assign	SEG_Sel = SYNTHESIZED_WIRE_17;




scan	b2v_inst(.EN_in1(SYNTHESIZED_WIRE_0),
.EN_in0(SYNTHESIZED_WIRE_1),.sdata(SYNTHESIZED_WIRE_21));

counter05	b2v_inst1(.C_CLK(SYNTHESIZED_WIRE_19),
.RST(Reset),.C_EN(SYNTHESIZED_WIRE_3),.C_out(SYNTHESIZED_WIRE_1),.D_OUT0(SYNTHESIZED_WIRE_11),.D_OUT1(SYNTHESIZED_WIRE_12));

fdiv1hz	b2v_inst11(.clk_in(SYNTHESIZED_WIRE_20),
.clk_out(SYNTHESIZED_WIRE_19));

fdiv1khz	b2v_inst12(.clk_in(CLK),
.clk_out(SYNTHESIZED_WIRE_20));

control	b2v_inst14(.SW1(SW),
.RST(Reset),.EN_in(SYNTHESIZED_WIRE_21),.Red1(Red1),.Red2(Red2),.Yellow1(Yellow1),.Yellow2(Yellow2),.Green1(Green1),.Green2(Green2));

counter55	b2v_inst2(.C_CLK(SYNTHESIZED_WIRE_19),
.RST(Reset),.C_EN(SYNTHESIZED_WIRE_7),.C_out(SYNTHESIZED_WIRE_0),.D_OUT0(SYNTHESIZED_WIRE_9),.D_OUT1(SYNTHESIZED_WIRE_10));

countersel	b2v_inst3(.D_IN(SYNTHESIZED_WIRE_21),
.D_OUT1(SYNTHESIZED_WIRE_7),.D_OUT0(SYNTHESIZED_WIRE_3));

datamux	b2v_inst6(.D_IN0(SYNTHESIZED_WIRE_9),
.D_IN1(SYNTHESIZED_WIRE_10),.D_IN2(SYNTHESIZED_WIRE_11),.D_IN3(SYNTHESIZED_WIRE_12),.SEL(SYNTHESIZED_WIRE_21),.D_OUT0(SYNTHESIZED_WIRE_15),.D_OUT1(SYNTHESIZED_WIRE_16));

dispdecoder	b2v_inst7(.data_in(SYNTHESIZED_WIRE_14),
.data_out(SEG_Data));

dispmux	b2v_inst8(.D_IN0(SYNTHESIZED_WIRE_15),
.D_IN1(SYNTHESIZED_WIRE_16),.SEL(SYNTHESIZED_WIRE_17),.D_OUT(SYNTHESIZED_WIRE_14));

dispselect	b2v_inst9(.CLK(SYNTHESIZED_WIRE_20),
.D_OUT(SYNTHESIZED_WIRE_17));


endmodule