dec643.c

TI DSP TMS320C643 McBSP源代码

/************************************************************
  Copyright (C), 2007 by SEED Electronic Technology LTD.
  FileName: DEC643.c
  Author:  Ya.X      Version : V1.0         Date:2007-09-20
  Description:   DEC643初始化  
*************************************************************/

#include <csl.h>
#include <csl_emifa.h>

#include "DEC643.h"

/* Initialize the board APIs */
void DEC643_init()
{
    volatile Uint32 test;
    
    EMIFA_Config emifaCfg0 = {
        EMIFA_FMKS(GBLCTL, EK2RATE, HALFCLK)    |
        EMIFA_FMKS(GBLCTL, EK2HZ, CLK)          |
        EMIFA_FMKS(GBLCTL, EK2EN, ENABLE)       |
        EMIFA_FMKS(GBLCTL, BRMODE, MRSTATUS)    |
        EMIFA_FMKS(GBLCTL, NOHOLD, DISABLE)     |
        EMIFA_FMKS(GBLCTL, EK1HZ, HIGHZ)        |
        EMIFA_FMKS(GBLCTL, EK1EN, ENABLE)       |
        EMIFA_FMKS(GBLCTL, CLK4EN, DISABLE)     |
        EMIFA_FMKS(GBLCTL, CLK6EN, DISABLE),
        
        EMIFA_FMKS(CECTL, WRSETUP, DEFAULT)    |
        EMIFA_FMKS(CECTL, WRSTRB, DEFAULT)     |
        EMIFA_FMKS(CECTL, WRHLD, DEFAULT)      |
        EMIFA_FMKS(CECTL, RDSETUP, DEFAULT)    |
        EMIFA_FMKS(CECTL, TA, DEFAULT)         |
        EMIFA_FMKS(CECTL, RDSTRB, DEFAULT)     |
        EMIFA_FMKS(CECTL, MTYPE, SDRAM64)      |
        EMIFA_FMKS(CECTL, WRHLDMSB, OF(1))     |
        EMIFA_FMKS(CECTL, RDHLD, OF(7)),
        
        EMIFA_FMKS(CECTL, WRSETUP, DEFAULT)    |
        EMIFA_FMKS(CECTL, WRSTRB, DEFAULT)     |
        EMIFA_FMKS(CECTL, WRHLD, DEFAULT)      |
        EMIFA_FMKS(CECTL, RDSETUP, DEFAULT)    |
        EMIFA_FMKS(CECTL, TA, DEFAULT)         |
        EMIFA_FMKS(CECTL, RDSTRB, DEFAULT)     |
        EMIFA_FMKS(CECTL, MTYPE, ASYNC8)       |
        EMIFA_FMKS(CECTL, RDHLD, DEFAULT),
        
        EMIFA_FMKS(CECTL, WRSETUP, OF(7))      |
        EMIFA_FMKS(CECTL, WRSTRB, OF(14))      |
        EMIFA_FMKS(CECTL, WRHLD, OF(2))        |
        EMIFA_FMKS(CECTL, RDSETUP, OF(2))      |
        EMIFA_FMKS(CECTL, TA, OF(2))           |
        EMIFA_FMKS(CECTL, RDSTRB, OF(14))      |
        EMIFA_FMKS(CECTL, MTYPE, ASYNC16)      |
        EMIFA_FMKS(CECTL, RDHLD, OF(1)),

        EMIFA_FMKS(CECTL, WRSETUP, OF(2))      |
        EMIFA_FMKS(CECTL, WRSTRB, OF(10))      |
        EMIFA_FMKS(CECTL, WRHLD, OF(2))        |
        EMIFA_FMKS(CECTL, RDSETUP, OF(2))      |
        EMIFA_FMKS(CECTL, TA, OF(2))           |
        EMIFA_FMKS(CECTL, RDSTRB, OF(10))      |
        EMIFA_FMKS(CECTL, MTYPE, SYNC32)       |
        EMIFA_FMKS(CECTL, RDHLD, OF(2)),
        
        EMIFA_FMKS(SDCTL, SDBSZ, 4BANKS)       |
        EMIFA_FMKS(SDCTL, SDRSZ, 12ROW)        |
        EMIFA_FMKS(SDCTL, SDCSZ, 8COL)         |
        EMIFA_FMKS(SDCTL, RFEN, ENABLE)        |
        EMIFA_FMKS(SDCTL, INIT, YES)           |
        EMIFA_FMKS(SDCTL, TRCD, OF(1))         |
        EMIFA_FMKS(SDCTL, TRP, OF(1))          |
        EMIFA_FMKS(SDCTL, TRC, OF(5))          |
        EMIFA_FMKS(SDCTL, SLFRFR, DISABLE),
        
        EMIFA_FMKS(SDTIM, XRFR, OF(0))         |
        EMIFA_FMKS(SDTIM, PERIOD, OF(2075)),
        
        EMIFA_FMKS(SDEXT, WR2RD, OF(1))        |
        EMIFA_FMKS(SDEXT, WR2DEAC, OF(3))      |
        EMIFA_FMKS(SDEXT, WR2WR, OF(1))        |
        EMIFA_FMKS(SDEXT, R2WDQM, OF(3))       |
        EMIFA_FMKS(SDEXT, RD2WR, OF(2))        |
        EMIFA_FMKS(SDEXT, RD2DEAC, OF(3))      |
        EMIFA_FMKS(SDEXT, RD2RD, OF(1))        |
        EMIFA_FMKS(SDEXT, THZP, OF(2))         |
        EMIFA_FMKS(SDEXT, TWR, OF(2))          |
        EMIFA_FMKS(SDEXT, TRRD, OF(0))         |
        EMIFA_FMKS(SDEXT, TRAS, OF(6))         |
        EMIFA_FMKS(SDEXT, TCL, OF(1)),           
        
        EMIFA_CESEC_DEFAULT,

        EMIFA_CESEC_DEFAULT,

        EMIFA_CESEC_DEFAULT,

        EMIFA_FMKS(CESEC, SNCCLK, ECLKOUT2)    |
        EMIFA_FMKS(CESEC, RENEN, READ)         |
        EMIFA_FMKS(CESEC, CEEXT, ACTIVE)       |
        EMIFA_FMKS(CESEC, SYNCWL, 0CYCLE)      |
        EMIFA_FMKS(CESEC, SYNCRL, 3CYCLE)
    };

    /* Initialize CSL */
    CSL_init();
    
    /* Unlock PERCFG through PCFGLOCK */
    *((unsigned long *)0x1b3f018) = 0x10c0010c;
    
    /* Enable VP0-VP2, I2C, McASP0 and McBSP in PERCFG */
    *((unsigned long *)0x1b3f000) = 0x7B;
    
    /* Read back PERCFG */
    test = *((unsigned long *)0x1b3f000);
    
    /* Wait at least 128 CPU cycles */
    DEC643_wait(128);

    /* Initialize EMIFA */
    EMIFA_config(&emifaCfg0);
}

/* Spin in a delay loop for delay iterations */
void DEC643_wait(Uint32 delay)
{
    volatile Uint32 i, n;
    
    n = 0;
    for (i = 0; i < delay; i++)
    {
        n = n + 1;
    }
}

/* Spin in a delay loop for delay microseconds */
void DEC643_waitusec(Uint32 delay)
{
    DEC643_wait(delay * 21);
}