📄 os_cpu_a.s
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* + 0x20 R9* + 0x24 R10* + 0x28 R11* + 0x2C R12* + 0x30 R13* + 0x34 R14* + 0x38 R15* + 0x3C R17* + 0x40 R18* + 0x44 R19* + 0x48 R20* + 0x4C R21* + 0x50 R22* + 0x54 R23* + 0x58 R24* + 0x5C R25* + 0x60 R26* + 0x64 R27* + 0x68 R28* + 0x6C R29* + 0x70 R30* + 0x74 R31 (HIGH MEMORY)** Note(s) : 1) If the task frame was saved by OSCtxSw(), IE would be set to 0.* If the task frame was saved by an ISR, IE would be set to 1.**********************************************************************************************************/OSIntCtxSw: BRLID r15, OSTaskSwHook /* Call OSTaskSwHook() */ AND r0, r0, r0 /* NO-OP */ LBUI r3, r0, OSPrioHighRdy /* OSPrioCur = OSPrioHighRdy */ SBI r3, r0, OSPrioCur LWI r3, r0, OSTCBHighRdy /* OSTCBCur = OSTCBHighRdy */ SWI r3, r0, OSTCBCur LW r1, r0, r3 /* SP = OSTCBHighRdy->OSTCBStkPtr */ LWI r31, r1, STK_OFFSET_R31 /* **************** RESTORE NEW TASK'S CONTEXT *************** */ LWI r30, r1, STK_OFFSET_R30 LWI r29, r1, STK_OFFSET_R29 LWI r28, r1, STK_OFFSET_R28 LWI r27, r1, STK_OFFSET_R27 LWI r26, r1, STK_OFFSET_R26 LWI r25, r1, STK_OFFSET_R25 LWI r24, r1, STK_OFFSET_R24 LWI r23, r1, STK_OFFSET_R23 LWI r22, r1, STK_OFFSET_R22 LWI r21, r1, STK_OFFSET_R21 LWI r20, r1, STK_OFFSET_R20 LWI r19, r1, STK_OFFSET_R19 LWI r18, r1, STK_OFFSET_R18 LWI r17, r1, STK_OFFSET_R17 LWI r15, r1, STK_OFFSET_R15 LWI r14, r1, STK_OFFSET_R14 LWI r13, r1, STK_OFFSET_R13 LWI r12, r1, STK_OFFSET_R12 LWI r11, r1, STK_OFFSET_R11 LWI r10, r1, STK_OFFSET_R10 LWI r9, r1, STK_OFFSET_R09 LWI r8, r1, STK_OFFSET_R08 LWI r7, r1, STK_OFFSET_R07 LWI r6, r1, STK_OFFSET_R06 LWI r5, r1, STK_OFFSET_R05 LWI r4, r1, STK_OFFSET_R04 LWI r2, r1, STK_OFFSET_R02 LWI r3, r1, STK_OFFSET_RMSR /* Get the saved RMSR */ ANDI r3, r3, CPU_IE_BIT /* See if IE is 0 (Saved by OSCtxSw()) or 1 (Saved by ISR) */ BNEI r3, OSIntCtxSw_SavedByISR /* Branch if ISR saved context */ /* *********** The context was saved by OSCtxSw() ************ */ LWI r3, r1, STK_OFFSET_RMSR /* Get the saved RMSR */ MTS RMSR,r3 LWI r3, r1, STK_OFFSET_R03 /* Restore R3 (was used a scratchpad register for RMSR) */ ADDIK r1, r1, STK_CTX_SIZE /* Clean up the stack (deallocate storage) */ RTSD r15, 8 /* Context was saved by OSCtxSw() */ AND r0, r0, r0 /* NO-OP */OSIntCtxSw_SavedByISR: /* ************ The context was saved by an ISR ************** */ LWI r3, r1, STK_OFFSET_RMSR /* Get the saved RMSR */ ANDNI r3, r3, CPU_IE_BIT /* Clear the IE bit (It will be set by the return from INT.) */ MTS RMSR,r3 LWI r3, r1, STK_OFFSET_R03 /* Restore R3 (was used a scratchpad register for RMSR) */ ADDIK r1, r1, STK_CTX_SIZE /* Clean up the stack (deallocate storage) */ RTID r14, 0 /* Context was saved by ISR, return address is in R14 */ AND r0, r0, r0 /* NO-OP *//*********************************************************************************************************** OS_CPU_ISR()** Description: This routine is intended to be the target of the Interrupt processing functionality that * occurs when the MicroBlaze is interrupted. The address, 'XOSExternalInterruptHandler', is * used as the branch destination in the code that is executed at addresses 0x10 and 0x14 in * the MicroBlaze vector table assuming that the vector table is in RAM* * The XPS interrupt vector is replaced by OS_CPU_ISR() by executing the code from a C function:** *(INT32U *)0x00000010 = 0xB0000000 | ((INT32U)OS_CPU_ISR >> 16);* *(INT32U *)0x00000014 = 0xB8080000 | ((INT32U)OS_CPU_ISR & 0x0000FFFF);** The interrupted task context is saved onto its stack as follows:** OSTCBCur->OSTCBStkPtr + 0x00 RMSR (See Note 1) (LOW Memory)* + 0x04 R2* + 0x08 R3* + 0x0C R4* + 0x10 R5 (p_arg passed to task)* + 0x14 R6* + 0x18 R7* + 0x1C R8* + 0x20 R9* + 0x24 R10* + 0x28 R11* + 0x2C R12* + 0x30 R13* + 0x34 R14* + 0x38 R15* + 0x3C R17* + 0x40 R18* + 0x44 R19* + 0x48 R20* + 0x4C R21* + 0x50 R22* + 0x54 R23* + 0x58 R24* + 0x5C R25* + 0x60 R26* + 0x64 R27* + 0x68 R28* + 0x6C R29* + 0x70 R30* + 0x74 R31 (HIGH MEMORY)** Note(s) : 1) The IE bit is saved onto the stack 'set' since the code must return to the interrupted* task with interrupts enabled.**********************************************************************************************************/_interrupt_handler:OS_CPU_ISR: /* ********** SAVE INTERRUPTED TASK'S CONTEXT *********** */ ADDIK r1, r1, -STK_CTX_SIZE /* Allocate storage for saving registers onto stack */ SWI r2, r1, STK_OFFSET_R02 SWI r3, r1, STK_OFFSET_R03 SWI r4, r1, STK_OFFSET_R04 SWI r5, r1, STK_OFFSET_R05 SWI r6, r1, STK_OFFSET_R06 SWI r7, r1, STK_OFFSET_R07 SWI r8, r1, STK_OFFSET_R08 SWI r9, r1, STK_OFFSET_R09 SWI r10, r1, STK_OFFSET_R10 SWI r11, r1, STK_OFFSET_R11 SWI r12, r1, STK_OFFSET_R12 SWI r13, r1, STK_OFFSET_R13 SWI r14, r1, STK_OFFSET_R14 SWI r15, r1, STK_OFFSET_R15 SWI r17, r1, STK_OFFSET_R17 SWI r18, r1, STK_OFFSET_R18 SWI r19, r1, STK_OFFSET_R19 SWI r20, r1, STK_OFFSET_R20 SWI r21, r1, STK_OFFSET_R21 SWI r22, r1, STK_OFFSET_R22 SWI r23, r1, STK_OFFSET_R23 SWI r24, r1, STK_OFFSET_R24 SWI r25, r1, STK_OFFSET_R25 SWI r26, r1, STK_OFFSET_R26 SWI r27, r1, STK_OFFSET_R27 SWI r28, r1, STK_OFFSET_R28 SWI r29, r1, STK_OFFSET_R29 SWI r30, r1, STK_OFFSET_R30 SWI r31, r1, STK_OFFSET_R31 MFS r3, RMSR /* save the MSR */ ORI r3, r3, CPU_IE_BIT /* Set IE to 1 to return to interrupted task with INT en. */ SWI r3, r1, STK_OFFSET_RMSR /* MSR is at top of frame */ LBUI r3, r0, OSIntNesting /* if (OSIntNesting == 0) { */ BNEI r3, OS_CPU_ISR_1 LWI r3, r0, OSTCBCur /* OSTCBCur->OSTCBStkPtr = SP */ SW r1, r0, r3 /* } */OS_CPU_ISR_1: LBUI r3, r0, OSIntNesting ADDIK r3, r3, 1 /* OSIntNesting++; */ SBI r3, r0, OSIntNesting BRLID r15, BSP_IntHandler /* Call the provided C level interrupt handler */ AND r0, r0, r0 /* NO-OP */ BRLID r15, OSIntExit /* OSIntExit() */ AND r0, r0, r0 /* NO-OP */ LWI r31, r1, STK_OFFSET_R31 /* ********* RESTORE INTERRUPTED TASK'S CONTEXT ********* */ LWI r30, r1, STK_OFFSET_R30 LWI r29, r1, STK_OFFSET_R29 LWI r28, r1, STK_OFFSET_R28 LWI r27, r1, STK_OFFSET_R27 LWI r26, r1, STK_OFFSET_R26 LWI r25, r1, STK_OFFSET_R25 LWI r24, r1, STK_OFFSET_R24 LWI r23, r1, STK_OFFSET_R23 LWI r22, r1, STK_OFFSET_R22 LWI r21, r1, STK_OFFSET_R21 LWI r20, r1, STK_OFFSET_R20 LWI r19, r1, STK_OFFSET_R19 LWI r18, r1, STK_OFFSET_R18 LWI r17, r1, STK_OFFSET_R17 LWI r15, r1, STK_OFFSET_R15 LWI r14, r1, STK_OFFSET_R14 LWI r13, r1, STK_OFFSET_R13 LWI r12, r1, STK_OFFSET_R12 LWI r11, r1, STK_OFFSET_R11 LWI r10, r1, STK_OFFSET_R10 LWI r9, r1, STK_OFFSET_R09 LWI r8, r1, STK_OFFSET_R08 LWI r7, r1, STK_OFFSET_R07 LWI r6, r1, STK_OFFSET_R06 LWI r5, r1, STK_OFFSET_R05 LWI r4, r1, STK_OFFSET_R04 LWI r2, r1, STK_OFFSET_R02 LWI r3, r1, STK_OFFSET_RMSR /* Get RMSR */ ANDNI r3, r3, CPU_IE_BIT /* Clear IE to prevent interrupts until stack is cleaned */ MTS RMSR,r3 LWI r3, r1, STK_OFFSET_R03 /* Restore R3 (was used a scratchpad register for RMSR) */ ADDIK r1, r1, STK_CTX_SIZE /* Clean up the stack */ RTID r14, 0 /* Return from interrupt with interrupts enabled */ AND r0, r0, r0 /* NO-OP */⌨️ 快捷键说明
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