arm.h

俄罗斯高人Mamaich的Pocket gcc编译器（运行在PocketPC上）的全部源代码。

/* Nonzero if we should compile for Thumb interworking.  */
#define ARM_FLAG_INTERWORK	(1 << 10)

/* Nonzero if we should have little-endian words even when compiling for
   big-endian (for backwards compatibility with older versions of GCC).  */
#define ARM_FLAG_LITTLE_WORDS	(1 << 11)

/* Nonzero if we need to protect the prolog from scheduling */
#define ARM_FLAG_NO_SCHED_PRO	(1 << 12)

/* Nonzero if a call to abort should be generated if a noreturn 
   function tries to return.  */
#define ARM_FLAG_ABORT_NORETURN	(1 << 13)

/* Nonzero if function prologues should not load the PIC register. */
#define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)

/* Nonzero if all call instructions should be indirect.  */
#define ARM_FLAG_LONG_CALLS	(1 << 15)
  
/* Nonzero means that the target ISA is the THUMB, not the ARM.  */
#define ARM_FLAG_THUMB          (1 << 16)

/* Set if a TPCS style stack frame should be generated, for non-leaf
   functions, even if they do not need one.  */
#define THUMB_FLAG_BACKTRACE	(1 << 17)

/* Set if a TPCS style stack frame should be generated, for leaf
   functions, even if they do not need one.  */
#define THUMB_FLAG_LEAF_BACKTRACE    		(1 << 18)

/* Set if externally visible functions should assume that they
   might be called in ARM mode, from a non-thumb aware code.  */
#define THUMB_FLAG_CALLEE_SUPER_INTERWORKING	(1 << 19)

/* Set if calls via function pointers should assume that their
   destination is non-Thumb aware.  */
#define THUMB_FLAG_CALLER_SUPER_INTERWORKING	(1 << 20)

/* Nonzero means target uses VFP FP.  */
#define ARM_FLAG_VFP		(1 << 21)

/* Nonzero means to use ARM/Thumb Procedure Call Standard conventions.  */
#define ARM_FLAG_ATPCS		(1 << 22)

#define TARGET_APCS_FRAME		(target_flags & ARM_FLAG_APCS_FRAME)
#define TARGET_POKE_FUNCTION_NAME	(target_flags & ARM_FLAG_POKE)
#define TARGET_FPE			(target_flags & ARM_FLAG_FPE)
#define TARGET_APCS_32			(target_flags & ARM_FLAG_APCS_32)
#define TARGET_APCS_STACK		(target_flags & ARM_FLAG_APCS_STACK)
#define TARGET_APCS_FLOAT		(target_flags & ARM_FLAG_APCS_FLOAT)
#define TARGET_APCS_REENT		(target_flags & ARM_FLAG_APCS_REENT)
#define TARGET_ATPCS			(target_flags & ARM_FLAG_ATPCS)
#define TARGET_MMU_TRAPS		(target_flags & ARM_FLAG_MMU_TRAPS)
#define TARGET_SOFT_FLOAT		(target_flags & ARM_FLAG_SOFT_FLOAT)
#define TARGET_HARD_FLOAT		(! TARGET_SOFT_FLOAT)
#define TARGET_VFP			(target_flags & ARM_FLAG_VFP)
#define TARGET_BIG_END			(target_flags & ARM_FLAG_BIG_END)
#define TARGET_INTERWORK		(target_flags & ARM_FLAG_INTERWORK)
#define TARGET_LITTLE_WORDS		(target_flags & ARM_FLAG_LITTLE_WORDS)
#define TARGET_NO_SCHED_PRO		(target_flags & ARM_FLAG_NO_SCHED_PRO)
#define TARGET_ABORT_NORETURN		(target_flags & ARM_FLAG_ABORT_NORETURN)
#define TARGET_SINGLE_PIC_BASE		(target_flags & ARM_FLAG_SINGLE_PIC_BASE)
#define TARGET_LONG_CALLS		(target_flags & ARM_FLAG_LONG_CALLS)
#define TARGET_THUMB                    (target_flags & ARM_FLAG_THUMB)
#define TARGET_ARM                      (! TARGET_THUMB)
#define TARGET_EITHER			1 /* (TARGET_ARM | TARGET_THUMB) */
#define TARGET_CALLEE_INTERWORKING	(target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
#define TARGET_CALLER_INTERWORKING	(target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
#define TARGET_BACKTRACE	        (leaf_function_p ()	      			\
				         ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE)	\
				         : (target_flags & THUMB_FLAG_BACKTRACE))

/* SUBTARGET_SWITCHES is used to add flags on a per-config basis.  */
#ifndef SUBTARGET_SWITCHES
#define SUBTARGET_SWITCHES
#endif

#define TARGET_SWITCHES							\
{									\
  {"apcs",			ARM_FLAG_APCS_FRAME, "" },		\
  {"apcs-frame",		ARM_FLAG_APCS_FRAME,			\
   N_("Generate APCS conformant stack frames") },			\
  {"no-apcs-frame",	       -ARM_FLAG_APCS_FRAME, "" },		\
  {"poke-function-name",	ARM_FLAG_POKE,				\
   N_("Store function names in object code") },				\
  {"no-poke-function-name",    -ARM_FLAG_POKE, "" },			\
  {"fpe",			ARM_FLAG_FPE,  "" },			\
  {"apcs-32",			ARM_FLAG_APCS_32,			\
   N_("Use the 32-bit version of the APCS") },				\
  {"apcs-26",		       -ARM_FLAG_APCS_32,			\
   N_("Use the 26-bit version of the APCS") },				\
  {"apcs-stack-check",		ARM_FLAG_APCS_STACK, "" },		\
  {"no-apcs-stack-check",      -ARM_FLAG_APCS_STACK, "" },		\
  {"apcs-float",		ARM_FLAG_APCS_FLOAT,			\
   N_("Pass FP arguments in FP registers") },				\
  {"no-apcs-float",	       -ARM_FLAG_APCS_FLOAT, "" },		\
  {"apcs-reentrant",		ARM_FLAG_APCS_REENT,			\
   N_("Generate re-entrant, PIC code") },				\
  {"no-apcs-reentrant",	       -ARM_FLAG_APCS_REENT, "" },		\
  {"alignment-traps",           ARM_FLAG_MMU_TRAPS,			\
   N_("The MMU will trap on unaligned accesses") },			\
  {"no-alignment-traps",       -ARM_FLAG_MMU_TRAPS, "" },		\
  {"short-load-bytes",		ARM_FLAG_MMU_TRAPS, "" },		\
  {"no-short-load-bytes",      -ARM_FLAG_MMU_TRAPS, "" },		\
  {"short-load-words",	       -ARM_FLAG_MMU_TRAPS, "" },		\
  {"no-short-load-words",	ARM_FLAG_MMU_TRAPS, "" },		\
  {"soft-float",		ARM_FLAG_SOFT_FLOAT,			\
   N_("Use library calls to perform FP operations") },			\
  {"hard-float",	       -ARM_FLAG_SOFT_FLOAT,			\
   N_("Use hardware floating point instructions") },			\
  {"big-endian",		ARM_FLAG_BIG_END,			\
   N_("Assume target CPU is configured as big endian") },		\
  {"little-endian",	       -ARM_FLAG_BIG_END,			\
   N_("Assume target CPU is configured as little endian") },		\
  {"words-little-endian",       ARM_FLAG_LITTLE_WORDS,			\
   N_("Assume big endian bytes, little endian words") },		\
  {"thumb-interwork",		ARM_FLAG_INTERWORK,			\
   N_("Support calls between Thumb and ARM instruction sets") },	\
  {"no-thumb-interwork",       -ARM_FLAG_INTERWORK, "" },		\
  {"abort-on-noreturn",         ARM_FLAG_ABORT_NORETURN,		\
   N_("Generate a call to abort if a noreturn function returns")},	\
  {"no-abort-on-noreturn",     -ARM_FLAG_ABORT_NORETURN, "" },		\
  {"no-sched-prolog",           ARM_FLAG_NO_SCHED_PRO,			\
   N_("Do not move instructions into a function's prologue") },		\
  {"sched-prolog",             -ARM_FLAG_NO_SCHED_PRO, "" },		\
  {"single-pic-base",		ARM_FLAG_SINGLE_PIC_BASE,		\
   N_("Do not load the PIC register in function prologues") },		\
  {"no-single-pic-base",       -ARM_FLAG_SINGLE_PIC_BASE, "" },		\
  {"long-calls",		ARM_FLAG_LONG_CALLS,			\
   N_("Generate call insns as indirect calls, if necessary") },		\
  {"no-long-calls",	       -ARM_FLAG_LONG_CALLS, "" },		\
  {"thumb",                     ARM_FLAG_THUMB,				\
   N_("Compile for the Thumb not the ARM") },				\
  {"no-thumb",                 -ARM_FLAG_THUMB, "" },			\
  {"arm",                      -ARM_FLAG_THUMB, "" },			\
  {"tpcs-frame",		    THUMB_FLAG_BACKTRACE,		\
   N_("Thumb: Generate (non-leaf) stack frames even if not needed") },	   \
  {"no-tpcs-frame",                -THUMB_FLAG_BACKTRACE, "" },		   \
  {"tpcs-leaf-frame",	  	    THUMB_FLAG_LEAF_BACKTRACE,		   \
   N_("Thumb: Generate (leaf) stack frames even if not needed") },	   \
  {"no-tpcs-leaf-frame",           -THUMB_FLAG_LEAF_BACKTRACE, "" },	   \
  {"callee-super-interworking",	    THUMB_FLAG_CALLEE_SUPER_INTERWORKING,  \
   N_("Thumb: Assume non-static functions may be called from ARM code") }, \
  {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING,  \
     "" },								   \
  {"caller-super-interworking",	    THUMB_FLAG_CALLER_SUPER_INTERWORKING,  \
   N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
  {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING,  \
   "" },								   \
  SUBTARGET_SWITCHES							   \
  {"",				TARGET_DEFAULT, "" }			   \
}

#define TARGET_OPTIONS						\
{								\
  {"cpu=",  & arm_select[0].string,				\
   N_("Specify the name of the target CPU") },			\
  {"arch=", & arm_select[1].string,				\
   N_("Specify the name of the target architecture") }, 	\
  {"tune=", & arm_select[2].string, "" }, 			\
  {"fpe=",  & target_fp_name, "" }, 				\
  {"fp=",   & target_fp_name,					\
   N_("Specify the version of the floating point emulator") },	\
  {"structure-size-boundary=", & structure_size_string, 	\
   N_("Specify the minimum bit alignment of structures") }, 	\
  {"pic-register=", & arm_pic_register_string,			\
   N_("Specify the register to be used for PIC addressing") }	\
}

struct arm_cpu_select
{
  const char *              string;
  const char *              name;
  const struct processors * processors;
};

/* This is a magic array.  If the user specifies a command line switch
   which matches one of the entries in TARGET_OPTIONS then the corresponding
   string pointer will be set to the value specified by the user.  */
extern struct arm_cpu_select arm_select[];

enum prog_mode_type
{
  prog_mode26,
  prog_mode32
};

/* Recast the program mode class to be the prog_mode attribute */
#define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)

extern enum prog_mode_type arm_prgmode;

/* What sort of floating point unit do we have? Hardware or software.
   If software, is it issue 2 or issue 3?  */
enum floating_point_type
{
  FP_HARD,
  FP_SOFT2,
  FP_SOFT3
};

/* Recast the floating point class to be the floating point attribute.  */
#define arm_fpu_attr ((enum attr_fpu) arm_fpu)

/* What type of floating point to tune for */
extern enum floating_point_type arm_fpu;

/* What type of floating point instructions are available */
extern enum floating_point_type arm_fpu_arch;

/* Default floating point architecture.  Override in sub-target if
   necessary.  */
#ifndef FP_DEFAULT
#define FP_DEFAULT FP_SOFT2
#endif

/* Nonzero if the processor has a fast multiply insn, and one that does
   a 64-bit multiply of two 32-bit values.  */
extern int arm_fast_multiply;

/* Nonzero if this chip supports the ARM Architecture 4 extensions */
extern int arm_arch4;

/* Nonzero if this chip supports the ARM Architecture 5 extensions */
extern int arm_arch5;

/* Nonzero if this chip supports the ARM Architecture 5E extensions */
extern int arm_arch5e;

/* Nonzero if this chip can benefit from load scheduling.  */
extern int arm_ld_sched;

/* Nonzero if generating thumb code.  */
extern int thumb_code;

/* Nonzero if this chip is a StrongARM.  */
extern int arm_is_strong;

/* Nonzero if this chip is an XScale.  */
extern int arm_is_xscale;

/* Nonzero if this chip is an ARM6 or an ARM7.  */
extern int arm_is_6_or_7;

#ifndef TARGET_DEFAULT
#define TARGET_DEFAULT  (ARM_FLAG_APCS_FRAME)
#endif

/* The frame pointer register used in gcc has nothing to do with debugging;
   that is controlled by the APCS-FRAME option.  */
#define CAN_DEBUG_WITHOUT_FP

#undef  TARGET_MEM_FUNCTIONS
#define TARGET_MEM_FUNCTIONS 1

#define OVERRIDE_OPTIONS  arm_override_options ()

/* Nonzero if PIC code requires explicit qualifiers to generate
   PLT and GOT relocs rather than the assembler doing so implicitly.
   Subtargets can override these if required.  */
#ifndef NEED_GOT_RELOC
#define NEED_GOT_RELOC	0
#endif
#ifndef NEED_PLT_RELOC
#define NEED_PLT_RELOC	0
#endif

/* Nonzero if we need to refer to the GOT with a PC-relative
   offset.  In other words, generate

   .word	_GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]  

   rather than

   .word	_GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)

   The default is true, which matches NetBSD.  Subtargets can 
   override this if required.  */
#ifndef GOT_PCREL
#define GOT_PCREL   1
#endif

/* Target machine storage Layout.  */


/* Define this macro if it is advisable to hold scalars in registers
   in a wider mode than that declared by the program.  In such cases,
   the value is constrained to be within the bounds of the declared
   type, but kept valid in the wider mode.  The signedness of the
   extension may differ from that of the type.  */

/* It is far faster to zero extend chars than to sign extend them */

#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)	\
  if (GET_MODE_CLASS (MODE) == MODE_INT		\
      && GET_MODE_SIZE (MODE) < 4)      	\
    {						\
      if (MODE == QImode)			\
	UNSIGNEDP = 1;				\
      else if (MODE == HImode)			\
	UNSIGNEDP = TARGET_MMU_TRAPS != 0;	\
      (MODE) = SImode;				\
    }

/* Define this macro if the promotion described by `PROMOTE_MODE'
   should also be done for outgoing function arguments.  */
/* This is required to ensure that push insns always push a word.  */
#define PROMOTE_FUNCTION_ARGS

/* For the ARM:
   I think I have added all the code to make this work.  Unfortunately,
   early releases of the floating point emulation code on RISCiX used a
   different format for extended precision numbers.  On my RISCiX box there
   is a bug somewhere which causes the machine to lock up when running enquire
   with long doubles.  There is the additional aspect that Norcroft C
   treats long doubles as doubles and we ought to remain compatible.
   Perhaps someone with an FPA coprocessor and not running RISCiX would like
   to try this someday. */
/* #define LONG_DOUBLE_TYPE_SIZE 96 */

/* Disable XFmode patterns in md file */
#define ENABLE_XF_PATTERNS 0

/* Define this if most significant bit is lowest numbered
   in instructions that operate on numbered bit-fields.  */
#define BITS_BIG_ENDIAN  0

/* Define this if most significant byte of a word is the lowest numbered.  
   Most ARM processors are run in little endian mode, so that is the default.
   If you want to have it run-time selectable, change the definition in a
   cover file to be TARGET_BIG_ENDIAN.  */