📄 hp-milli.s
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.entry; The subtract is not nullified since it does no harm and can be used; by the two cases that branch back to "normal". comib,>= 15,arg1,special_divisor sub r0,arg1,temp ; clear carry, negate the divisor ds r0,temp,r0 ; set V-bit to 1normal: add arg0,arg0,retreg ; shift msb bit into carry ds r0,arg1,temp ; 1st divide step, if no carry addc retreg,retreg,retreg ; shift retreg with/into carry ds temp,arg1,temp ; 2nd divide step addc retreg,retreg,retreg ; shift retreg with/into carry ds temp,arg1,temp ; 3rd divide step addc retreg,retreg,retreg ; shift retreg with/into carry ds temp,arg1,temp ; 4th divide step addc retreg,retreg,retreg ; shift retreg with/into carry ds temp,arg1,temp ; 5th divide step addc retreg,retreg,retreg ; shift retreg with/into carry ds temp,arg1,temp ; 6th divide step addc retreg,retreg,retreg ; shift retreg with/into carry ds temp,arg1,temp ; 7th divide step addc retreg,retreg,retreg ; shift retreg with/into carry ds temp,arg1,temp ; 8th divide step addc retreg,retreg,retreg ; shift retreg with/into carry ds temp,arg1,temp ; 9th divide step addc retreg,retreg,retreg ; shift retreg with/into carry ds temp,arg1,temp ; 10th divide step addc retreg,retreg,retreg ; shift retreg with/into carry ds temp,arg1,temp ; 11th divide step addc retreg,retreg,retreg ; shift retreg with/into carry ds temp,arg1,temp ; 12th divide step addc retreg,retreg,retreg ; shift retreg with/into carry ds temp,arg1,temp ; 13th divide step addc retreg,retreg,retreg ; shift retreg with/into carry ds temp,arg1,temp ; 14th divide step addc retreg,retreg,retreg ; shift retreg with/into carry ds temp,arg1,temp ; 15th divide step addc retreg,retreg,retreg ; shift retreg with/into carry ds temp,arg1,temp ; 16th divide step addc retreg,retreg,retreg ; shift retreg with/into carry ds temp,arg1,temp ; 17th divide step addc retreg,retreg,retreg ; shift retreg with/into carry ds temp,arg1,temp ; 18th divide step addc retreg,retreg,retreg ; shift retreg with/into carry ds temp,arg1,temp ; 19th divide step addc retreg,retreg,retreg ; shift retreg with/into carry ds temp,arg1,temp ; 20th divide step addc retreg,retreg,retreg ; shift retreg with/into carry ds temp,arg1,temp ; 21st divide step addc retreg,retreg,retreg ; shift retreg with/into carry ds temp,arg1,temp ; 22nd divide step addc retreg,retreg,retreg ; shift retreg with/into carry ds temp,arg1,temp ; 23rd divide step addc retreg,retreg,retreg ; shift retreg with/into carry ds temp,arg1,temp ; 24th divide step addc retreg,retreg,retreg ; shift retreg with/into carry ds temp,arg1,temp ; 25th divide step addc retreg,retreg,retreg ; shift retreg with/into carry ds temp,arg1,temp ; 26th divide step addc retreg,retreg,retreg ; shift retreg with/into carry ds temp,arg1,temp ; 27th divide step addc retreg,retreg,retreg ; shift retreg with/into carry ds temp,arg1,temp ; 28th divide step addc retreg,retreg,retreg ; shift retreg with/into carry ds temp,arg1,temp ; 29th divide step addc retreg,retreg,retreg ; shift retreg with/into carry ds temp,arg1,temp ; 30th divide step addc retreg,retreg,retreg ; shift retreg with/into carry ds temp,arg1,temp ; 31st divide step addc retreg,retreg,retreg ; shift retreg with/into carry ds temp,arg1,temp ; 32nd divide step, bv 0(r31) addc retreg,retreg,retreg ; shift last retreg bit into retreg;_____________________________________________________________________________; handle the cases where divisor is a small constant or has high bit onspecial_divisor: comib,> 0,arg1,big_divisor nop blr arg1,r0 nopzero_divisor: ; this label is here to provide external visibility addit,= 0,arg1,0 ; trap for zero dvr nop bv 0(r31) ; divisor == 1 copy arg0,retreg bv 0(r31) ; divisor == 2 extru arg0,30,31,retreg b,n $$divU_3 ; divisor == 3 nop bv 0(r31) ; divisor == 4 extru arg0,29,30,retreg b,n $$divU_5 ; divisor == 5 nop b,n $$divU_6 ; divisor == 6 nop b,n $$divU_7 ; divisor == 7 nop bv 0(r31) ; divisor == 8 extru arg0,28,29,retreg b,n $$divU_9 ; divisor == 9 nop b,n $$divU_10 ; divisor == 10 nop b normal ; divisor == 11 ds r0,temp,r0 ; set V-bit to 1 b,n $$divU_12 ; divisor == 12 nop b normal ; divisor == 13 ds r0,temp,r0 ; set V-bit to 1 b,n $$divU_14 ; divisor == 14 nop b,n $$divU_15 ; divisor == 15 nop;_____________________________________________________________________________; Handle the case where the high bit is on in the divisor.; Compute: if( dividend>=divisor) quotient=1; else quotient=0;; Note: dividend>==divisor iff dividend-divisor does not borrow; and not borrow iff carrybig_divisor: sub arg0,arg1,r0 bv 0(r31) addc r0,r0,retreg .exit .procend .endt2: .EQU r1; x2 .EQU arg0 ; r26t1: .EQU arg1 ; r25; x1 .EQU ret1 ; r29;_____________________________________________________________________________$$divide_by_constant: .PROC .CALLINFO millicode .entry .export $$divide_by_constant,millicode; Provides a "nice" label for the code covered by the unwind descriptor; for things like gprof.$$divI_2: .EXPORT $$divI_2,MILLICODE COMCLR,>= arg0,0,0 ADDI 1,arg0,arg0 bv 0(r31) EXTRS arg0,30,31,ret1$$divI_4: .EXPORT $$divI_4,MILLICODE COMCLR,>= arg0,0,0 ADDI 3,arg0,arg0 bv 0(r31) EXTRS arg0,29,30,ret1$$divI_8: .EXPORT $$divI_8,MILLICODE COMCLR,>= arg0,0,0 ADDI 7,arg0,arg0 bv 0(r31) EXTRS arg0,28,29,ret1$$divI_16: .EXPORT $$divI_16,MILLICODE COMCLR,>= arg0,0,0 ADDI 15,arg0,arg0 bv 0(r31) EXTRS arg0,27,28,ret1$$divI_3: .EXPORT $$divI_3,MILLICODE COMB,<,N arg0,0,$neg3 ADDI 1,arg0,arg0 EXTRU arg0,1,2,ret1 SH2ADD arg0,arg0,arg0 B $pos ADDC ret1,0,ret1$neg3: SUBI 1,arg0,arg0 EXTRU arg0,1,2,ret1 SH2ADD arg0,arg0,arg0 B $neg ADDC ret1,0,ret1$$divU_3: .EXPORT $$divU_3,MILLICODE ADDI 1,arg0,arg0 ADDC 0,0,ret1 SHD ret1,arg0,30,t1 SH2ADD arg0,arg0,arg0 B $pos ADDC ret1,t1,ret1$$divI_5: .EXPORT $$divI_5,MILLICODE COMB,<,N arg0,0,$neg5 ADDI 3,arg0,t1 SH1ADD arg0,t1,arg0 B $pos ADDC 0,0,ret1$neg5: SUB 0,arg0,arg0 ADDI 1,arg0,arg0 SHD 0,arg0,31,ret1 SH1ADD arg0,arg0,arg0 B $neg ADDC ret1,0,ret1$$divU_5: .EXPORT $$divU_5,MILLICODE ADDI 1,arg0,arg0 ADDC 0,0,ret1 SHD ret1,arg0,31,t1 SH1ADD arg0,arg0,arg0 B $pos ADDC t1,ret1,ret1$$divI_6: .EXPORT $$divI_6,MILLICODE COMB,<,N arg0,0,$neg6 EXTRU arg0,30,31,arg0 ADDI 5,arg0,t1 SH2ADD arg0,t1,arg0 B $pos ADDC 0,0,ret1$neg6: SUBI 2,arg0,arg0 EXTRU arg0,30,31,arg0 SHD 0,arg0,30,ret1 SH2ADD arg0,arg0,arg0 B $neg ADDC ret1,0,ret1$$divU_6: .EXPORT $$divU_6,MILLICODE EXTRU arg0,30,31,arg0 ADDI 1,arg0,arg0 SHD 0,arg0,30,ret1 SH2ADD arg0,arg0,arg0 B $pos ADDC ret1,0,ret1$$divU_10: .EXPORT $$divU_10,MILLICODE EXTRU arg0,30,31,arg0 ADDI 3,arg0,t1 SH1ADD arg0,t1,arg0 ADDC 0,0,ret1$pos: SHD ret1,arg0,28,t1 SHD arg0,0,28,t2 ADD arg0,t2,arg0 ADDC ret1,t1,ret1$pos_for_17: SHD ret1,arg0,24,t1 SHD arg0,0,24,t2 ADD arg0,t2,arg0 ADDC ret1,t1,ret1 SHD ret1,arg0,16,t1 SHD arg0,0,16,t2 ADD arg0,t2,arg0 bv 0(r31) ADDC ret1,t1,ret1$$divI_10: .EXPORT $$divI_10,MILLICODE COMB,< arg0,0,$neg10 COPY 0,ret1 EXTRU arg0,30,31,arg0 ADDIB,TR 1,arg0,$pos SH1ADD arg0,arg0,arg0 $neg10: SUBI 2,arg0,arg0 EXTRU arg0,30,31,arg0 SH1ADD arg0,arg0,arg0 $neg: SHD ret1,arg0,28,t1 SHD arg0,0,28,t2 ADD arg0,t2,arg0 ADDC ret1,t1,ret1$neg_for_17: SHD ret1,arg0,24,t1 SHD arg0,0,24,t2 ADD arg0,t2,arg0 ADDC ret1,t1,ret1 SHD ret1,arg0,16,t1 SHD arg0,0,16,t2 ADD arg0,t2,arg0 ADDC ret1,t1,ret1 bv 0(r31) SUB 0,ret1,ret1$$divI_12: .EXPORT $$divI_12,MILLICODE COMB,< arg0,0,$neg12 COPY 0,ret1 EXTRU arg0,29,30,arg0 ADDIB,TR 1,arg0,$pos SH2ADD arg0,arg0,arg0 $neg12: SUBI 4,arg0,arg0 EXTRU arg0,29,30,arg0 B $neg SH2ADD arg0,arg0,arg0 $$divU_12: .EXPORT $$divU_12,MILLICODE EXTRU arg0,29,30,arg0 ADDI 5,arg0,t1 SH2ADD arg0,t1,arg0 B $pos ADDC 0,0,ret1$$divI_15: .EXPORT $$divI_15,MILLICODE COMB,< arg0,0,$neg15 COPY 0,ret1 ADDIB,TR 1,arg0,$pos+4 SHD ret1,arg0,28,t1$neg15: B $neg SUBI 1,arg0,arg0$$divU_15: .EXPORT $$divU_15,MILLICODE ADDI 1,arg0,arg0 B $pos ADDC 0,0,ret1$$divI_17: .EXPORT $$divI_17,MILLICODE COMB,<,N arg0,0,$neg17 ADDI 1,arg0,arg0 SHD 0,arg0,28,t1 SHD arg0,0,28,t2 SUB t2,arg0,arg0 B $pos_for_17 SUBB t1,0,ret1$neg17: SUBI 1,arg0,arg0 SHD 0,arg0,28,t1 SHD arg0,0,28,t2 SUB t2,arg0,arg0 B $neg_for_17 SUBB t1,0,ret1$$divU_17: .EXPORT $$divU_17,MILLICODE ADDI 1,arg0,arg0 ADDC 0,0,ret1 SHD ret1,arg0,28,t1 $u17: SHD arg0,0,28,t2 SUB t2,arg0,arg0 B $pos_for_17 SUBB t1,ret1,ret1$$divI_7: .EXPORT $$divI_7,MILLICODE COMB,<,N arg0,0,$neg7$7: ADDI 1,arg0,arg0 SHD 0,arg0,29,ret1 SH3ADD arg0,arg0,arg0 ADDC ret1,0,ret1$pos7: SHD ret1,arg0,26,t1 SHD arg0,0,26,t2 ADD arg0,t2,arg0 ADDC ret1,t1,ret1 SHD ret1,arg0,20,t1 SHD arg0,0,20,t2 ADD arg0,t2,arg0 ADDC ret1,t1,t1 COPY 0,ret1 SHD,= t1,arg0,24,t1 $1: ADDB,TR t1,ret1,$2 EXTRU arg0,31,24,arg0 bv,n 0(r31)$2: ADDB,TR t1,arg0,$1 EXTRU,= arg0,7,8,t1 $neg7: SUBI 1,arg0,arg0 $8: SHD 0,arg0,29,ret1 SH3ADD arg0,arg0,arg0 ADDC ret1,0,ret1$neg7_shift: SHD ret1,arg0,26,t1 SHD arg0,0,26,t2 ADD arg0,t2,arg0 ADDC ret1,t1,ret1 SHD ret1,arg0,20,t1 SHD arg0,0,20,t2 ADD arg0,t2,arg0 ADDC ret1,t1,t1 COPY 0,ret1 SHD,= t1,arg0,24,t1 $3: ADDB,TR t1,ret1,$4 EXTRU arg0,31,24,arg0 ⌨️ 快捷键说明
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