maverick.c

俄罗斯高人Mamaich的Pocket gcc编译器（运行在PocketPC上）的全部源代码。

  MCRC2 (mv ## insname, cpnum, 0, 1, opcode2, \
	 armreg (12), mvreg (regDSPname, 16))

/* Define a move from a DSP register to a DSP accumulator.  */
#define MVDSPACC(insname, opcode2, regDSPname) \
  MCRC2 (mv ## insname, 6, 0, 1, opcode2, acreg (0), mvreg (regDSPname, 16))

/* Define a move from a DSP accumulator to a DSP register.  */
#define MVACCDSP(insname, opcode2, regDSPname) \
  MCRC2 (mv ## insname, 6, 0, 0, opcode2, mvreg (regDSPname, 0), acreg (16))

/* Define move insns between a float DSP register and an ARM
 * register.  */
#define MVf(nameAD, nameDA, opcode2) \
  MVDSPARM (nameAD, 4, opcode2, "f"); \
  MVARMDSP (nameDA, 4, opcode2, "f")

/* Define move insns between a double DSP register and an ARM
 * register.  */
#define MVd(nameAD, nameDA, opcode2) \
  MVDSPARM (nameAD, 4, opcode2, "d"); \
  MVARMDSP (nameDA, 4, opcode2, "d")

/* Define move insns between a 32-bit integer DSP register and an ARM
 * register.  */
#define MVfx(nameAD, nameDA, opcode2) \
  MVDSPARM (nameAD, 5, opcode2, "fx"); \
  MVARMDSP (nameDA, 5, opcode2, "fx")

/* Define move insns between a 64-bit integer DSP register and an ARM
 * register.  */
#define MVdx(nameAD, nameDA, opcode2) \
  MVDSPARM (nameAD, 5, opcode2, "dx"); \
  MVARMDSP (nameDA, 5, opcode2, "dx")

/* Define move insns between a 32-bit DSP register and a DSP
 * accumulator.  */
#define MVfxa(nameFA, nameAF, opcode2) \
  MVDSPACC (nameFA, opcode2, "fx"); \
  MVACCDSP (nameAF, opcode2, "fx")

/* Define move insns between a 64-bit DSP register and a DSP
 * accumulator.  */
#define MVdxa(nameDA, nameAD, opcode2) \
  MVDSPACC (nameDA, opcode2, "dx"); \
  MVACCDSP (nameAD, opcode2, "dx")

/* Produce the insn identifiers for a pair of mv insns.  */
#define insns_MV(name1, name2) \
  insn (mv ## name1), insn (mv ## name2)

/* Define a MCR or MRC instruction with three register operands.  */
#define MCRC3(insname, cpnum, opcode1, dir, opcode2, reg1spec, reg2spec, reg3spec) \
  mv_insn (insname, , \
	   ((14<<24)|((opcode1)<<21)|((dir)<<20)| \
	    ((cpnum)<<8)|((opcode2)<<5)|(1<<4)), \
	   reg1spec, comma, reg2spec, comma, reg3spec, \
	   tick_random)

/* Define all load_store insns.  */
LDSTall (ldrs, 4, 1, 0, "f");
LDSTall (ldrd, 4, 1, 1, "d");
LDSTall (ldr32, 5, 1, 0, "fx");
LDSTall (ldr64, 5, 1, 1, "dx");
LDSTall (strs, 4, 0, 0, "f");
LDSTall (strd, 4, 0, 1, "d");
LDSTall (str32, 5, 0, 0, "fx");
LDSTall (str64, 5, 0, 1, "dx");

/* Create the load_store insn group.  */
func *load_store_insns[] = {
  insns_LDSTall (ldrs),  insns_LDSTall (ldrd),
  insns_LDSTall (ldr32), insns_LDSTall (ldr64),
  insns_LDSTall (strs),  insns_LDSTall (strd),
  insns_LDSTall (str32), insns_LDSTall (str64),
  0
};

/* Define all move insns.  */
MVf (sr, rs, 2);
MVd (dlr, rdl, 0);
MVd (dhr, rdh, 1);
MVdx (64lr, r64l, 0);
MVdx (64hr, r64h, 1);
MVfxa (al32, 32al, 0);
MVfxa (am32, 32am, 1);
MVfxa (ah32, 32ah, 2);
MVfxa (a32, 32a, 3);
MVdxa (a64, 64a, 4);
MCRC2 (mvsc32, 6, 0, 1, 5, dspsc, mvreg ("fx", 16));
MCRC2 (mv32sc, 6, 0, 0, 5, mvreg ("fx", 0), dspsc);
CDP2 (cpys, , 4, 0, 0, "f", "f");
CDP2 (cpyd, , 4, 0, 1, "d", "d");

/* Create the move insns group.  */
func *move_insns[] = {
  insns_MV (sr, rs), insns_MV (dlr, rdl), insns_MV (dhr, rdh),
  insns_MV (64lr, r64l), insns_MV (64hr, r64h),
  insns_MV (al32, 32al), insns_MV (am32, 32am), insns_MV (ah32, 32ah),
  insns_MV (a32, 32a), insns_MV (a64, 64a),
  insn (mvsc32), insn (mv32sc), insn (cpys), insn (cpyd),
  0
};

/* Define all conversion insns.  */
CDP2 (cvtsd, , 4, 0, 3, "d", "f");
CDP2 (cvtds, , 4, 0, 2, "f", "d");
CDP2 (cvt32s, , 4, 0, 4, "f", "fx");
CDP2 (cvt32d, , 4, 0, 5, "d", "fx");
CDP2 (cvt64s, , 4, 0, 6, "f", "dx");
CDP2 (cvt64d, , 4, 0, 7, "d", "dx");
CDP2 (cvts32, , 5, 1, 4, "fx", "f");
CDP2 (cvtd32, , 5, 1, 5, "fx", "d");
CDP2 (truncs32, , 5, 1, 6, "fx", "f");
CDP2 (truncd32, , 5, 1, 7, "fx", "d");

/* Create the conv insns group.  */
func *conv_insns[] = {
  insn (cvtsd), insn (cvtds), insn (cvt32s), insn (cvt32d),
  insn (cvt64s), insn (cvt64d), insn (cvts32), insn (cvtd32),
  insn (truncs32), insn (truncd32),
  0
};

/* Define all shift insns.  */
MCRC3 (rshl32, 5, 0, 0, 2, mvreg ("fx", 16), mvreg ("fx", 0), armreg(12));
MCRC3 (rshl64, 5, 0, 0, 3, mvreg ("dx", 16), mvreg ("dx", 0), armreg(12));
CDP2_imm7 (sh32, 5, 0, "fx", "fx");
CDP2_imm7 (sh64, 5, 2, "dx", "dx");

/* Create the shift insns group.  */
func *shift_insns[] = {
  insn (rshl32), insn (rshl64),
  insn (sh32), insn (sh64),
  0
};

/* Define all comparison insns.  */
MCRC3 (cmps, 4, 0, 1, 4, armreg (12), mvreg ("f", 16), mvreg ("f", 0));
MCRC3 (cmpd, 4, 0, 1, 5, armreg (12), mvreg ("d", 16), mvreg ("d", 0));
MCRC3 (cmp32, 5, 0, 1, 4, armreg (12), mvreg ("fx", 16), mvreg ("fx", 0));
MCRC3 (cmp64, 5, 0, 1, 5, armreg (12), mvreg ("dx", 16), mvreg ("dx", 0));

/* Create the comp insns group.  */
func *comp_insns[] = {
  insn (cmps), insn (cmpd),
  insn (cmp32), insn (cmp64),
  0
};

/* Define all floating-point arithmetic insns.  */
CDP2f (abs, 3, 0);
CDP2d (abs, 3, 1);
CDP2f (neg, 3, 2);
CDP2d (neg, 3, 3);
CDP3f (add, 3, 4);
CDP3d (add, 3, 5);
CDP3f (sub, 3, 6);
CDP3d (sub, 3, 7);
CDP3f (mul, 1, 0);
CDP3d (mul, 1, 1);

/* Create the fp-arith insns group.  */
func *fp_arith_insns[] = {
  CDPfp_insns (abs), CDPfp_insns (neg),
  CDPfp_insns (add), CDPfp_insns (sub), CDPfp_insns (mul),
  0
};

/* Define all integer arithmetic insns.  */
CDP2fx (abs, 3, 0);
CDP2dx (abs, 3, 1);
CDP2fx (neg, 3, 2);
CDP2dx (neg, 3, 3);
CDP3fx (add, 3, 4);
CDP3dx (add, 3, 5);
CDP3fx (sub, 3, 6);
CDP3dx (sub, 3, 7);
CDP3fx (mul, 1, 0);
CDP3dx (mul, 1, 1);
CDP3fx (mac, 1, 2);
CDP3fx (msc, 1, 3);

/* Create the int-arith insns group.  */
func *int_arith_insns[] = {
  CDPx_insns (abs), CDPx_insns (neg),
  CDPx_insns (add), CDPx_insns (sub), CDPx_insns (mul),
  insn (mac32), insn (msc32),
  0
};

/* Define all accumulator arithmetic insns.  */
CDP41A (madd32, 0);
CDP41A (msub32, 1);
CDP42A (madda32, 2);
CDP42A (msuba32, 3);

/* Create the acc-arith insns group.  */
func *acc_arith_insns[] = {
  insn (madd32), insn (msub32),
  insn (madda32), insn (msuba32),
  0
};

/* Create the set of all groups.  */
group_t
groups[] = {
  { "load_store", load_store_insns },
  { "move", move_insns },
  { "conv", conv_insns },
  { "shift", shift_insns },
  { "comp", comp_insns },
  { "fp_arith", fp_arith_insns },
  { "int_arith", int_arith_insns },
  { "acc_arith", acc_arith_insns },
  { 0 }
};

int
main(int argc, char *argv[])
{
  FILE *as_in = stdout, *dis_out = stderr;

  /* Check whether we're filtering insns.  */
  if (argc > 1)
    skip_list = argv + 1;

  /* Output assembler header.  */
  fputs ("\t.text\n"
	 "\t.align\n",
	 as_in);
  /* Output comments for the testsuite-driver and the initial
   * disassembler output. */
  fputs ("#objdump: -dr --prefix-address --show-raw-insn\n"
	 "#name: Maverick\n"
	 "#as: -marm9e\n"
	 "\n"
	 "# Test the instructions of Maverick\n"
	 "\n"
	 ".*: +file format.*arm.*\n"
	 "\n"
	 "Disassembly of section .text:\n",
	 dis_out);

  /* Now emit all (selected) insns.  */
  output_groups (groups, as_in, dis_out);

  exit (0);
}