📄 tc-arm.c
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#define CP_T_WB 0x00200000#define CONDS_BIT 0x00100000#define LOAD_BIT 0x00100000#define DOUBLE_LOAD_FLAG 0x00000001struct asm_cond{ const char * template; unsigned long value;};#define COND_ALWAYS 0xe0000000#define COND_MASK 0xf0000000static const struct asm_cond conds[] ={ {"eq", 0x00000000}, {"ne", 0x10000000}, {"cs", 0x20000000}, {"hs", 0x20000000}, {"cc", 0x30000000}, {"ul", 0x30000000}, {"lo", 0x30000000}, {"mi", 0x40000000}, {"pl", 0x50000000}, {"vs", 0x60000000}, {"vc", 0x70000000}, {"hi", 0x80000000}, {"ls", 0x90000000}, {"ge", 0xa0000000}, {"lt", 0xb0000000}, {"gt", 0xc0000000}, {"le", 0xd0000000}, {"al", 0xe0000000}, {"nv", 0xf0000000}};struct asm_psr{ const char * template; boolean cpsr; unsigned long field;};/* The bit that distnguishes CPSR and SPSR. */#define SPSR_BIT (1 << 22)/* How many bits to shift the PSR_xxx bits up by. */#define PSR_SHIFT 16#define PSR_c (1 << 0)#define PSR_x (1 << 1)#define PSR_s (1 << 2)#define PSR_f (1 << 3)static const struct asm_psr psrs[] ={ {"CPSR", true, PSR_c | PSR_f}, {"CPSR_all", true, PSR_c | PSR_f}, {"SPSR", false, PSR_c | PSR_f}, {"SPSR_all", false, PSR_c | PSR_f}, {"CPSR_flg", true, PSR_f}, {"CPSR_f", true, PSR_f}, {"SPSR_flg", false, PSR_f}, {"SPSR_f", false, PSR_f}, {"CPSR_c", true, PSR_c}, {"CPSR_ctl", true, PSR_c}, {"SPSR_c", false, PSR_c}, {"SPSR_ctl", false, PSR_c}, {"CPSR_x", true, PSR_x}, {"CPSR_s", true, PSR_s}, {"SPSR_x", false, PSR_x}, {"SPSR_s", false, PSR_s}, /* Combinations of flags. */ {"CPSR_fs", true, PSR_f | PSR_s}, {"CPSR_fx", true, PSR_f | PSR_x}, {"CPSR_fc", true, PSR_f | PSR_c}, {"CPSR_sf", true, PSR_s | PSR_f}, {"CPSR_sx", true, PSR_s | PSR_x}, {"CPSR_sc", true, PSR_s | PSR_c}, {"CPSR_xf", true, PSR_x | PSR_f}, {"CPSR_xs", true, PSR_x | PSR_s}, {"CPSR_xc", true, PSR_x | PSR_c}, {"CPSR_cf", true, PSR_c | PSR_f}, {"CPSR_cs", true, PSR_c | PSR_s}, {"CPSR_cx", true, PSR_c | PSR_x}, {"CPSR_fsx", true, PSR_f | PSR_s | PSR_x}, {"CPSR_fsc", true, PSR_f | PSR_s | PSR_c}, {"CPSR_fxs", true, PSR_f | PSR_x | PSR_s}, {"CPSR_fxc", true, PSR_f | PSR_x | PSR_c}, {"CPSR_fcs", true, PSR_f | PSR_c | PSR_s}, {"CPSR_fcx", true, PSR_f | PSR_c | PSR_x}, {"CPSR_sfx", true, PSR_s | PSR_f | PSR_x}, {"CPSR_sfc", true, PSR_s | PSR_f | PSR_c}, {"CPSR_sxf", true, PSR_s | PSR_x | PSR_f}, {"CPSR_sxc", true, PSR_s | PSR_x | PSR_c}, {"CPSR_scf", true, PSR_s | PSR_c | PSR_f}, {"CPSR_scx", true, PSR_s | PSR_c | PSR_x}, {"CPSR_xfs", true, PSR_x | PSR_f | PSR_s}, {"CPSR_xfc", true, PSR_x | PSR_f | PSR_c}, {"CPSR_xsf", true, PSR_x | PSR_s | PSR_f}, {"CPSR_xsc", true, PSR_x | PSR_s | PSR_c}, {"CPSR_xcf", true, PSR_x | PSR_c | PSR_f}, {"CPSR_xcs", true, PSR_x | PSR_c | PSR_s}, {"CPSR_cfs", true, PSR_c | PSR_f | PSR_s}, {"CPSR_cfx", true, PSR_c | PSR_f | PSR_x}, {"CPSR_csf", true, PSR_c | PSR_s | PSR_f}, {"CPSR_csx", true, PSR_c | PSR_s | PSR_x}, {"CPSR_cxf", true, PSR_c | PSR_x | PSR_f}, {"CPSR_cxs", true, PSR_c | PSR_x | PSR_s}, {"CPSR_fsxc", true, PSR_f | PSR_s | PSR_x | PSR_c}, {"CPSR_fscx", true, PSR_f | PSR_s | PSR_c | PSR_x}, {"CPSR_fxsc", true, PSR_f | PSR_x | PSR_s | PSR_c}, {"CPSR_fxcs", true, PSR_f | PSR_x | PSR_c | PSR_s}, {"CPSR_fcsx", true, PSR_f | PSR_c | PSR_s | PSR_x}, {"CPSR_fcxs", true, PSR_f | PSR_c | PSR_x | PSR_s}, {"CPSR_sfxc", true, PSR_s | PSR_f | PSR_x | PSR_c}, {"CPSR_sfcx", true, PSR_s | PSR_f | PSR_c | PSR_x}, {"CPSR_sxfc", true, PSR_s | PSR_x | PSR_f | PSR_c}, {"CPSR_sxcf", true, PSR_s | PSR_x | PSR_c | PSR_f}, {"CPSR_scfx", true, PSR_s | PSR_c | PSR_f | PSR_x}, {"CPSR_scxf", true, PSR_s | PSR_c | PSR_x | PSR_f}, {"CPSR_xfsc", true, PSR_x | PSR_f | PSR_s | PSR_c}, {"CPSR_xfcs", true, PSR_x | PSR_f | PSR_c | PSR_s}, {"CPSR_xsfc", true, PSR_x | PSR_s | PSR_f | PSR_c}, {"CPSR_xscf", true, PSR_x | PSR_s | PSR_c | PSR_f}, {"CPSR_xcfs", true, PSR_x | PSR_c | PSR_f | PSR_s}, {"CPSR_xcsf", true, PSR_x | PSR_c | PSR_s | PSR_f}, {"CPSR_cfsx", true, PSR_c | PSR_f | PSR_s | PSR_x}, {"CPSR_cfxs", true, PSR_c | PSR_f | PSR_x | PSR_s}, {"CPSR_csfx", true, PSR_c | PSR_s | PSR_f | PSR_x}, {"CPSR_csxf", true, PSR_c | PSR_s | PSR_x | PSR_f}, {"CPSR_cxfs", true, PSR_c | PSR_x | PSR_f | PSR_s}, {"CPSR_cxsf", true, PSR_c | PSR_x | PSR_s | PSR_f}, {"SPSR_fs", false, PSR_f | PSR_s}, {"SPSR_fx", false, PSR_f | PSR_x}, {"SPSR_fc", false, PSR_f | PSR_c}, {"SPSR_sf", false, PSR_s | PSR_f}, {"SPSR_sx", false, PSR_s | PSR_x}, {"SPSR_sc", false, PSR_s | PSR_c}, {"SPSR_xf", false, PSR_x | PSR_f}, {"SPSR_xs", false, PSR_x | PSR_s}, {"SPSR_xc", false, PSR_x | PSR_c}, {"SPSR_cf", false, PSR_c | PSR_f}, {"SPSR_cs", false, PSR_c | PSR_s}, {"SPSR_cx", false, PSR_c | PSR_x}, {"SPSR_fsx", false, PSR_f | PSR_s | PSR_x}, {"SPSR_fsc", false, PSR_f | PSR_s | PSR_c}, {"SPSR_fxs", false, PSR_f | PSR_x | PSR_s}, {"SPSR_fxc", false, PSR_f | PSR_x | PSR_c}, {"SPSR_fcs", false, PSR_f | PSR_c | PSR_s}, {"SPSR_fcx", false, PSR_f | PSR_c | PSR_x}, {"SPSR_sfx", false, PSR_s | PSR_f | PSR_x}, {"SPSR_sfc", false, PSR_s | PSR_f | PSR_c}, {"SPSR_sxf", false, PSR_s | PSR_x | PSR_f}, {"SPSR_sxc", false, PSR_s | PSR_x | PSR_c}, {"SPSR_scf", false, PSR_s | PSR_c | PSR_f}, {"SPSR_scx", false, PSR_s | PSR_c | PSR_x}, {"SPSR_xfs", false, PSR_x | PSR_f | PSR_s}, {"SPSR_xfc", false, PSR_x | PSR_f | PSR_c}, {"SPSR_xsf", false, PSR_x | PSR_s | PSR_f}, {"SPSR_xsc", false, PSR_x | PSR_s | PSR_c}, {"SPSR_xcf", false, PSR_x | PSR_c | PSR_f}, {"SPSR_xcs", false, PSR_x | PSR_c | PSR_s}, {"SPSR_cfs", false, PSR_c | PSR_f | PSR_s}, {"SPSR_cfx", false, PSR_c | PSR_f | PSR_x}, {"SPSR_csf", false, PSR_c | PSR_s | PSR_f}, {"SPSR_csx", false, PSR_c | PSR_s | PSR_x}, {"SPSR_cxf", false, PSR_c | PSR_x | PSR_f}, {"SPSR_cxs", false, PSR_c | PSR_x | PSR_s}, {"SPSR_fsxc", false, PSR_f | PSR_s | PSR_x | PSR_c}, {"SPSR_fscx", false, PSR_f | PSR_s | PSR_c | PSR_x}, {"SPSR_fxsc", false, PSR_f | PSR_x | PSR_s | PSR_c}, {"SPSR_fxcs", false, PSR_f | PSR_x | PSR_c | PSR_s}, {"SPSR_fcsx", false, PSR_f | PSR_c | PSR_s | PSR_x}, {"SPSR_fcxs", false, PSR_f | PSR_c | PSR_x | PSR_s}, {"SPSR_sfxc", false, PSR_s | PSR_f | PSR_x | PSR_c}, {"SPSR_sfcx", false, PSR_s | PSR_f | PSR_c | PSR_x}, {"SPSR_sxfc", false, PSR_s | PSR_x | PSR_f | PSR_c}, {"SPSR_sxcf", false, PSR_s | PSR_x | PSR_c | PSR_f}, {"SPSR_scfx", false, PSR_s | PSR_c | PSR_f | PSR_x}, {"SPSR_scxf", false, PSR_s | PSR_c | PSR_x | PSR_f}, {"SPSR_xfsc", false, PSR_x | PSR_f | PSR_s | PSR_c}, {"SPSR_xfcs", false, PSR_x | PSR_f | PSR_c | PSR_s}, {"SPSR_xsfc", false, PSR_x | PSR_s | PSR_f | PSR_c}, {"SPSR_xscf", false, PSR_x | PSR_s | PSR_c | PSR_f}, {"SPSR_xcfs", false, PSR_x | PSR_c | PSR_f | PSR_s}, {"SPSR_xcsf", false, PSR_x | PSR_c | PSR_s | PSR_f}, {"SPSR_cfsx", false, PSR_c | PSR_f | PSR_s | PSR_x}, {"SPSR_cfxs", false, PSR_c | PSR_f | PSR_x | PSR_s}, {"SPSR_csfx", false, PSR_c | PSR_s | PSR_f | PSR_x}, {"SPSR_csxf", false, PSR_c | PSR_s | PSR_x | PSR_f}, {"SPSR_cxfs", false, PSR_c | PSR_x | PSR_f | PSR_s}, {"SPSR_cxsf", false, PSR_c | PSR_x | PSR_s | PSR_f},};enum vfp_dp_reg_pos{ VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn};enum vfp_sp_reg_pos{ VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn};enum vfp_ldstm_type{ VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX};/* VFP system registers. */struct vfp_reg{ const char *name; unsigned long regno;};static const struct vfp_reg vfp_regs[] ={ {"fpsid", 0x00000000}, {"FPSID", 0x00000000}, {"fpscr", 0x00010000}, {"FPSCR", 0x00010000}, {"fpexc", 0x00080000}, {"FPEXC", 0x00080000}};/* Structure for a hash table entry for a register. */struct reg_entry{ const char * name; int number;};/* Some well known registers that we refer to directly elsewhere. */#define REG_SP 13#define REG_LR 14#define REG_PC 15/* These are the standard names. Users can add aliases with .req. *//* Integer Register Numbers. */static const struct reg_entry rn_table[] ={ {"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, {"r12", 12}, {"r13", REG_SP}, {"r14", REG_LR}, {"r15", REG_PC}, /* ATPCS Synonyms. */ {"a1", 0}, {"a2", 1}, {"a3", 2}, {"a4", 3}, {"v1", 4}, {"v2", 5}, {"v3", 6}, {"v4", 7}, {"v5", 8}, {"v6", 9}, {"v7", 10}, {"v8", 11}, /* Well-known aliases. */ {"wr", 7}, {"sb", 9}, {"sl", 10}, {"fp", 11}, {"ip", 12}, {"sp", REG_SP}, {"lr", REG_LR}, {"pc", REG_PC}, {NULL, 0}};/* Co-processor Numbers. */static const struct reg_entry cp_table[] ={ {"p0", 0}, {"p1", 1}, {"p2", 2}, {"p3", 3}, {"p4", 4}, {"p5", 5}, {"p6", 6}, {"p7", 7}, {"p8", 8}, {"p9", 9}, {"p10", 10}, {"p11", 11}, {"p12", 12}, {"p13", 13}, {"p14", 14}, {"p15", 15}, {NULL, 0}};/* Co-processor Register Numbers. */static const struct reg_entry cn_table[] ={ {"c0", 0}, {"c1", 1}, {"c2", 2}, {"c3", 3}, {"c4", 4}, {"c5", 5}, {"c6", 6}, {"c7", 7}, {"c8", 8}, {"c9", 9}, {"c10", 10}, {"c11", 11}, {"c12", 12}, {"c13", 13}, {"c14", 14}, {"c15", 15}, /* Not really valid, but kept for back-wards compatibility. */ {"cr0", 0}, {"cr1", 1}, {"cr2", 2}, {"cr3", 3}, {"cr4", 4}, {"cr5", 5}, {"cr6", 6}, {"cr7", 7}, {"cr8", 8}, {"cr9", 9}, {"cr10", 10}, {"cr11", 11}, {"cr12", 12}, {"cr13", 13}, {"cr14", 14}, {"cr15", 15}, {NULL, 0}};/* FPA Registers. */static const struct reg_entry fn_table[] ={ {"f0", 0}, {"f1", 1}, {"f2", 2}, {"f3", 3}, {"f4", 4}, {"f5", 5}, {"f6", 6}, {"f7", 7}, {NULL, 0}};/* VFP SP Registers. */static const struct reg_entry sn_table[] ={ {"s0", 0}, {"s1", 1}, {"s2", 2}, {"s3", 3}, {"s4", 4}, {"s5", 5}, {"s6", 6}, {"s7", 7}, {"s8", 8}, {"s9", 9}, {"s10", 10}, {"s11", 11}, {"s12", 12}, {"s13", 13}, {"s14", 14}, {"s15", 15}, {"s16", 16}, {"s17", 17}, {"s18", 18}, {"s19", 19}, {"s20", 20}, {"s21", 21}, {"s22", 22}, {"s23", 23}, {"s24", 24}, {"s25", 25}, {"s26", 26}, {"s27", 27}, {"s28", 28}, {"s29", 29}, {"s30", 30}, {"s31", 31}, {NULL, 0}};/* VFP DP Registers. */
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