dynamic_clock.c
来自「MMI层OBJ不能完全编译」· C语言 代码 · 共 775 行 · 第 1/2 页
C
775 行
(FLASH_WAIT_STATE << 11) |
(FLASH_RDY_POLARITY << 10) | (1 << 9) |
(FLASH_RDY << 8) | (1 << 7) | (1 << 6) |
(FLASH_BURST_WRAP << 3) |
FLASH_BURST_LENGTH);
// Configure EMIF for burst operation:
SET_EMIF_CONF_REG(0, 0, 0, 0, 0); // (WP, FLUSH_PREFETCH, PREFETCH_MODE, PDE, PWD_EN)
SET_EMIF_NO_DYN_WAIT(3, 0);
SET_EMIF_ADVANCED_CFG(3, 1, 0, 0, 0, 0, 2);// SET_EMIF_ADVANCED_CFG(CS, RC, CLKMSK, BTMODE, ADVHOLD, OEHOLD, OESETUP)
SET_EMIF_CFG(3, 2, 1, 1, 2, 3, 0, 1); // SET_EMIF_CFG(CS, BTWST, MEMMODE, WELEN, WRWST, RDWST, RT, FCLKDIV)
asm(" NOP");
asm(" NOP");
asm(" NOP");
asm(" NOP");
asm(" NOP");
asm(" NOP");
asm(" NOP");
asm(" NOP");
MEM16 (0xfffffb02) = 0x00;
MEM16 (0xfffffb02) = 0x13;
asm(" NOP");
asm(" NOP");
asm(" NOP");
asm(" NOP");
asm(" NOP");
asm(" NOP");
asm(" NOP");
asm(" NOP");
}
extern UWORD16 flash_device_id;
void enable_burst_flash()
{
void (*burst_enable)(void);
if(0x7E == flash_device_id)
{
burst_enable = enable_flash_burst;
}
else
{
burst_enable = enable_flash_burst_mirror;
}
(*burst_enable)();
}
//fangcj added: ___________________________________________________
#if 1
SYS_UWORD16 read_ps_ram_bcr_reg()
{
MEM16 (PSRAM_OFFSET + 0x007FFFF0);
MEM16 (PSRAM_OFFSET + 0x007FFFFE);
MEM16 (PSRAM_OFFSET + 0x007FFFFE);
MEM16 (PSRAM_OFFSET + 0x007FFFFE) = 0x0001;
return (MEM16(PSRAM_OFFSET + 0x007FFFFE));
}
SYS_UWORD16 read_flash_bcr_reg()
{
SYS_UWORD16 read_reg;
#if 0
MEM16(FLASH_OFFSET_ADR + 0x555) = 0xAA;
MEM16(FLASH_OFFSET_ADR + 0x2AA) = 0x55;
MEM16(FLASH_OFFSET_ADR + 0x555) = 0xC6;
read_reg = MEM16(FLASH_OFFSET_ADR + 0x0);
MEM16(FLASH_OFFSET_ADR + 0) = 0xF0;//reset state
return read_reg;
#else
FLASH_WR(FLASH_OFFSET_ADR, LLD_UNLOCK_ADDR1, NOR_UNLOCK_DATA1);
FLASH_WR(FLASH_OFFSET_ADR, LLD_UNLOCK_ADDR2, NOR_UNLOCK_DATA2);
FLASH_WR(FLASH_OFFSET_ADR, LLD_UNLOCK_ADDR1, WSXXX_SET_CONFIG_DATA);
read_reg = FLASH_RD(FLASH_OFFSET_ADR, 0x0);
FLASH_WR(FLASH_OFFSET_ADR, 0x0, 0xF0);//reset flash state
return read_reg;
#endif
}
#endif
/*
* Before to call the function, the application must:
* - Check that DSP is in IDLE3 before to modify PARAM
*/
/*---------------------------------------------------------*/
/* f_dynamic_clock_cfg() */
/*---------------------------------------------------------*/
/* Description : This function realizes the dynamic clock */
/* configuration changing DPLL, ARM and DSP */
/* clocks for Samson and Calypso families */
/* */
/* Input: d_clock_cfg => num of selected clock */
/* configuration */
/* */
/*---------------------------------------------------------*/
f_dynamic_clock_cfg(SYS_UWORD8 d_clock_cfg) {
/*
* Local variable used to check the selected clock configuration exist
* and is inside the array of clock configurations.
* It must be initialized to 0.
*/
SYS_UWORD8 d_array_index=0;
static SYS_UWORD8 d_first_call = 1;
T_PARAM_MCU_DSP *p_mcu_dsp_param = (T_PARAM_MCU_DSP *) PARAM_ADR;
#if (CHIPSET==15)
T_EMIF_CONF emif_conf = {
C_EMIF_PREFETCH_INSTRUCTION,
C_EMIF_PDE_ENABLE,
C_EMIF_PWD_ENABLE,
0,
0};
#endif
/*
* FOR DEBUG ONLY : use of GPIO_0 to check change of clock
* depending on DSP or/and ARM clock activity
*/
// (*( volatile UWORD16* )(0xFFFEF008)) &= 0xFFFE; // ASIC_CONF_REG
// (*( volatile UWORD16* )(0xFFFE4806)) |= 0x0020; // Enable ARMIO clock
// (*( volatile UWORD16* )(0xFFFE4802)) |= 0x0001; // GPIO_0=1
// (*( volatile UWORD16* )(0xFFFE4804)) &= 0xFFFE; // GPIO_0=output
p_dynamic_clock_cfg = (T_DYNAMIC_CLOCK_CFG *)a_dynamic_clock_cfg[d_array_index];
while ((p_dynamic_clock_cfg != NULL) && (d_array_index < C_NB_MAX_CLOCK_CONFIG))
{
if (p_dynamic_clock_cfg->d_clock_cfg_index == d_clock_cfg)
break;
p_dynamic_clock_cfg = (T_DYNAMIC_CLOCK_CFG *)a_dynamic_clock_cfg[++d_array_index];
}
/*
* Check that the configuration is valid
* if not valid, current clock configuration stays unchanged
*/
if ((p_dynamic_clock_cfg != NULL) && (d_array_index < C_NB_MAX_CLOCK_CONFIG))
{
/*
* Save and mask all interrupts configuration
*/
/* Fix for SRS - Startup Restart Syndrome */
if( d_first_call != 1)
{
OS_system_protect();
//INT_DisableIRQ();
old_int_mask = NU_Control_Interrupts( NU_DISABLE_INTERRUPTS );
}
#if (CODE_VERSION != SIMULATION)
/*
* Securise access to DPLL registers for SAMSON chip
*/
#if (CHIPSET == 4)
/*
* Force access factor on strobe 0 to 2 in order to secure
* the access on DPLL register
*/
RHEA_INITRHEA(2,0,0x7F); // should be 0xFE02
#elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) ||(CHIPSET == 15)
/*
* Configure RHEA Access Factor for Strobe 0 and Strobe 1.
* Configure also RHEA timeout.
*/
RHEA_INITRHEA(p_dynamic_clock_cfg->d_rhea_af_strobe0, \
p_dynamic_clock_cfg->d_rhea_af_strobe1, \
p_dynamic_clock_cfg->d_rhea_timeout);
#else
RHEA_INITRHEA(0,0,0x7F); // should be 0xFE00 due to no DMA limitation at 34MHz
// Must be updated according to ARM clock configuration
#endif
/*
* DSP latencies configuration
* if increase DSP clock
*/
if (p_dynamic_clock_cfg->d_dsp_clk > d_dsp_cur_clk)
{
p_mcu_dsp_param->d_transfer_rate = p_dynamic_clock_cfg->d_transfer_rate;
p_mcu_dsp_param->d_lat_mcu_bridge = p_dynamic_clock_cfg->d_lat_mcu_bridge;
p_mcu_dsp_param->d_lat_mcu_hom2sam = p_dynamic_clock_cfg->d_lat_mcu_hom2sam;
p_mcu_dsp_param->d_lat_mcu_bef_fast_access = p_dynamic_clock_cfg->d_lat_mcu_bef_fast_access;
p_mcu_dsp_param->d_lat_dsp_after_sam = p_dynamic_clock_cfg->d_lat_dsp_after_sam;
}
/*
* Force the DPLL is Bypass mode
*/
DPLL_RESET_PLL_ENABLE;
/*
* Wait that DPLL enters in Bypass mode
*/
while(DPLL_READ_DPLL_LOCK == DPLL_LOCK) {}
/*
* Configure DPLL BYPASS mode
*/
DPLL_INIT_BYPASS_MODE(p_dynamic_clock_cfg->d_bypass_div);
/*
* Configure DPLL clock frequency
*/
DPLL_INIT_DPLL_CLOCK(p_dynamic_clock_cfg->d_dpll_div, p_dynamic_clock_cfg->d_dpll_mult);
/*
* Configure DSP clock frequency
*/
#if (CHIPSET == 12)
CLKM_DSP_DIV_FACTOR(p_dynamic_clock_cfg->d_dsp_div_clk);
#endif
/*
* Configure ARM clock source and Frequency
*/
#if (CHIPSET == 15)
CLKM_InitARMClock(p_dynamic_clock_cfg->d_arm_clk_source,
p_dynamic_clock_cfg->d_arm_clk_mode);
#else
CLKM_InitARMClock(p_dynamic_clock_cfg->d_arm_clk_source,
p_dynamic_clock_cfg->d_arm_clk_div,
p_dynamic_clock_cfg->d_arm_clk_div_sel);
#endif
/*
* Configure ARM External Memory (wait-state, Dummy-cycle,...)
*/
#if (CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)
MEM_INIT_CS0(p_dynamic_clock_cfg->d_cs0.d_ws, p_dynamic_clock_cfg->d_cs0.d_dvs, p_dynamic_clock_cfg->d_cs0.d_we, p_dynamic_clock_cfg->d_cs0.d_dc);
MEM_INIT_CS1(p_dynamic_clock_cfg->d_cs1.d_ws, p_dynamic_clock_cfg->d_cs1.d_dvs, p_dynamic_clock_cfg->d_cs1.d_we, p_dynamic_clock_cfg->d_cs1.d_dc);
MEM_INIT_CS2(p_dynamic_clock_cfg->d_cs2.d_ws, p_dynamic_clock_cfg->d_cs2.d_dvs, p_dynamic_clock_cfg->d_cs2.d_we, p_dynamic_clock_cfg->d_cs2.d_dc);
MEM_INIT_CS3(p_dynamic_clock_cfg->d_cs3.d_ws, p_dynamic_clock_cfg->d_cs3.d_dvs, p_dynamic_clock_cfg->d_cs3.d_we, p_dynamic_clock_cfg->d_cs3.d_dc);
MEM_INIT_CS4(p_dynamic_clock_cfg->d_cs4.d_ws, p_dynamic_clock_cfg->d_cs4.d_dvs, p_dynamic_clock_cfg->d_cs4.d_we, p_dynamic_clock_cfg->d_cs4.d_dc);
#elif (CHIPSET == 12)
f_memif_init_cs(0,(T_MEMIF_CS_CONFIG *)& p_dynamic_clock_cfg->d_cs0);
f_memif_init_cs(4,(T_MEMIF_CS_CONFIG *)& p_dynamic_clock_cfg->d_cs4);
f_memif_init_cs(5,(T_MEMIF_CS_CONFIG *)& p_dynamic_clock_cfg->d_cs5);
#elif (CHIPSET == 15)
f_emif_set_priority(C_EMIF_DEFAULT_DMA_ACCESS, C_EMIF_DEFAULT_MCU_ACCESS);
//f_emif_set_conf(&emif_conf);
//f_emif_cs_mode(0,(T_EMIF_CS_CONFIG *)& p_dynamic_clock_cfg->d_cs0);
//f_emif_cs_mode(3,(T_EMIF_CS_CONFIG *)& p_dynamic_clock_cfg->d_cs3);
#else
#error "This CHIPSET configuration is not supported"
#endif
/*
* Configure ARM Internal Memory (wait-state, Dummy-cycle,...)
*/
#if (CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)
/* Internal SRAM */
MEM_INIT_CS6(p_dynamic_clock_cfg->d_cs6.d_ws, p_dynamic_clock_cfg->d_cs6.d_dvs, p_dynamic_clock_cfg->d_cs6.d_we, p_dynamic_clock_cfg->d_cs6.d_dc);
/* Internal BOOT ROM */
MEM_INIT_CS7(p_dynamic_clock_cfg->d_cs7.d_ws, p_dynamic_clock_cfg->d_cs7.d_dvs, p_dynamic_clock_cfg->d_cs7.d_we, p_dynamic_clock_cfg->d_cs7.d_dc);
#elif (CHIPSET == 12) || (CHIPSET == 15)
/* Nothing to do because configuration is hard-coded */
#else
#error "This CHIPSET configuration is not supported"
#endif
/*
* Configure API wait-state for HOM and SAM mode
*
* 1 WS in SAM mode when DSP = 78MHz and MCU=39MHz
* or DSP =104Mhz and MCU=52Mhz
* Always 0 WS in HOM mode for MCU frequency up to and
* including 39 MHz (52Mhz for c035)
* 1 WS in HOM mode to workaround HW bug 3504
* dma_arbtrs > Concurrent access to API from DMA and MCU
*/
RHEA_INITAPI(p_dynamic_clock_cfg->d_api_ws_hom, p_dynamic_clock_cfg->d_api_ws_sam);
/*
* Force the DPLL in Locked mode
*/
DPLL_SET_PLL_ENABLE;
/*
* Wait that DPLL enters in Locked mode
*/
while(DPLL_READ_DPLL_LOCK != DPLL_LOCK) {}
/*
* Configure RHEA Access Factor for Strobe 0 and Strobe 1.
* Configure also RHEA timeout.
* For SAMSON only, for Calypso, it's been configure before DPLL bypass.
*/
#if (CHIPSET == 4)
RHEA_INITRHEA(p_dynamic_clock_cfg->d_rhea_af_strobe0, \
p_dynamic_clock_cfg->d_rhea_af_strobe1, \
p_dynamic_clock_cfg->d_rhea_timeout);
#endif
#endif /* CODE_VERSION != SIMULATION */
#if (PSP_STANDALONE == 0)
/*
* Re-initialize gauging processing: this part of code is done in l1_initialize()
* function during L1 init.
*/
l1_dpll_init_var();
/*
* Power management variables
*/
l1_pwr_mgt_init();
#endif
/*
* Re-initialize ARM wait loop: during init phase, this function is called in
* l1_initialize() function
*/
initialize_wait_loop();
/*
* DSP latencies configuration
* if decrease DSP clock
*/
if (p_dynamic_clock_cfg->d_dsp_clk <= d_dsp_cur_clk)
{
p_mcu_dsp_param->d_transfer_rate = p_dynamic_clock_cfg->d_transfer_rate;
p_mcu_dsp_param->d_lat_mcu_bridge = p_dynamic_clock_cfg->d_lat_mcu_bridge;
p_mcu_dsp_param->d_lat_mcu_hom2sam = p_dynamic_clock_cfg->d_lat_mcu_hom2sam;
p_mcu_dsp_param->d_lat_mcu_bef_fast_access = p_dynamic_clock_cfg->d_lat_mcu_bef_fast_access;
p_mcu_dsp_param->d_lat_dsp_after_sam = p_dynamic_clock_cfg->d_lat_dsp_after_sam;
}
/*
* Save new current DSP clock
*/
d_dsp_cur_clk = p_dynamic_clock_cfg->d_dsp_clk;
/*
* Restore all interrupts
*/
/* Fix for SRS - Startup Restart Syndrome */
if( d_first_call != 1)
{
OS_system_Unprotect();
//INT_EnableIRQ();
NU_Control_Interrupts( old_int_mask );
}
else
d_first_call = 2;
/*
* FOR DEBUG ONLY : use of GPIO_0 to check change of clock
* depending on DSP or/and ARM clock activity
*/
// (*( volatile UWORD16* )(0xFFFEF008)) &= 0xFFFE; // ASIC_CONF_REG
// (*( volatile UWORD16* )(0xFFFE4804)) &= 0xFFFE; // GPIO_0=output
// (*( volatile UWORD16* )(0xFFFE4802)) &= 0xFFFE; // GPIO_0=0
// (*( volatile UWORD16* )(0xFFFE4806)) &= ~0x0020; // Disable ARMIO clock
} /* ((p_dynamic_clock_cfg != NULL) && (d_tab_index < C_NB_CLOCK_CONFIG)) */
} /* f_dynamic_clock_cfg() */
#endif /* SAMSON/CALYPSO families */
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