📄 dynamic_clock_12.h
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// should be 0xFE00 due to no DMA limitation at 34MHz
// Must be updated according to ARM clock configuration
// Timeout must be set to 0xFF for chipset
// Calypso C035 at 52MHz
0, 0,
/* RHEA Timeout */
0xFF,
/* EMIF configuration */
/* structure used for CHIPSET 12 is different, see definition in sys_memif.h */
/* new memif drivers integrate new features as Page mode */
#if (BOARD == 6)
// CS0
{
/* CONF_CS0 register configuration */
5,C_MEMIF_DVS_16,C_MEMIF_WRITE_EN,0,C_MEMIF_RODC_DIS,C_MEMIF_WRDC_DIS,C_MEMIF_WWS_VALUE_EN,
/* EXWS_CS0 register configuration */
C_MEMIF_PAGE_MODE_DIS,C_MEMIF_PMS_4B,15,15,
/* DCCTRL_CS0 register configuration */
C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS
},
// CS4
{
/* CONF_CS4 register configuration */
5,C_MEMIF_DVS_16,C_MEMIF_WRITE_EN,0,C_MEMIF_RODC_DIS,C_MEMIF_WRDC_DIS,C_MEMIF_WWS_VALUE_EN,
/* EXWS_CS4 register configuration */
C_MEMIF_PAGE_MODE_DIS,C_MEMIF_PMS_4B,15,15,
/* DCCTRL_CS4 register configuration */
C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS
},
// CS5
{
/* CONF_CS5 register configuration */
5,C_MEMIF_DVS_16,C_MEMIF_WRITE_EN,0,C_MEMIF_RODC_DIS,C_MEMIF_WRDC_DIS,C_MEMIF_WWS_VALUE_EN,
/* EXWS_CS5 register configuration */
C_MEMIF_PAGE_MODE_DIS,C_MEMIF_PMS_4B,15,15,
/* DCCTRL_CS5 register configuration */
C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS
},
// BOARD == 6
#elif (BOARD == 42) // E-Sample SRAM
// CS0
{
/* CONF_CS0 register configuration */
4,C_MEMIF_DVS_16,C_MEMIF_WRITE_EN,0,C_MEMIF_RODC_DIS,C_MEMIF_WRDC_DIS,C_MEMIF_WWS_VALUE_EN,
/* EXWS_CS0 register configuration */
C_MEMIF_PAGE_MODE_DIS,C_MEMIF_PMS_4B,15,15,
/* DCCTRL_CS0 register configuration */
C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS
},
// CS4 - FLASH
{
/* CONF_CS4 register configuration */
4,C_MEMIF_DVS_16,C_MEMIF_WRITE_EN,0,C_MEMIF_RODC_DIS,C_MEMIF_WRDC_DIS,C_MEMIF_WWS_VALUE_EN,
/* EXWS_CS4 register configuration */
C_MEMIF_PAGE_MODE_DIS,C_MEMIF_PMS_4B,15,15,
/* DCCTRL_CS4 register configuration */
C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS
},
// CS5 - External SRAM
{
/* CONF_CS5 register configuration */
4,C_MEMIF_DVS_16,C_MEMIF_WRITE_EN,0,C_MEMIF_RODC_DIS,C_MEMIF_WRDC_DIS,C_MEMIF_WWS_VALUE_EN,
/* EXWS_CS5 register configuration */
C_MEMIF_PAGE_MODE_DIS,C_MEMIF_PMS_4B,15,15,
/* DCCTRL_CS5 register configuration */
C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS
},
// BOARD == 42
#elif (BOARD == 43) // E-Sample FLASH
// CS0
{
/* CONF_CS0 register configuration */
4,C_MEMIF_DVS_16,C_MEMIF_WRITE_EN,0,C_MEMIF_RODC_DIS,C_MEMIF_WRDC_DIS,C_MEMIF_WWS_VALUE_EN,
/* EXWS_CS0 register configuration */
C_MEMIF_PAGE_MODE_DIS,C_MEMIF_PMS_4B,15,15,
/* DCCTRL_CS0 register configuration */
C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS
},
// CS4 - External SRAM
{
/* CONF_CS4 register configuration */
4,C_MEMIF_DVS_16,C_MEMIF_WRITE_EN,0,C_MEMIF_RODC_DIS,C_MEMIF_WRDC_DIS,C_MEMIF_WWS_VALUE_EN,
/* EXWS_CS4 register configuration */
C_MEMIF_PAGE_MODE_DIS,C_MEMIF_PMS_4B,15,15,
/* DCCTRL_CS4 register configuration */
C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS
},
// CS5 - FLASH
{
/* CONF_CS5 register configuration */
4,C_MEMIF_DVS_16,C_MEMIF_WRITE_EN,0,C_MEMIF_RODC_DIS,C_MEMIF_WRDC_DIS,C_MEMIF_WWS_VALUE_EN,
/* EXWS_CS5 register configuration */
C_MEMIF_PAGE_MODE_EN,C_MEMIF_PMS_16B,2,15,
/* DCCTRL_CS5 register configuration */
C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS
},
// BOARD == 43
#elif (BOARD == 45) // EVA-Conso FLASH
// Not validated
// CS0
{
/* CONF_CS0 register configuration */
6,C_MEMIF_DVS_16,C_MEMIF_WRITE_EN,0,C_MEMIF_RODC_DIS,C_MEMIF_WRDC_DIS,C_MEMIF_WWS_VALUE_EN,
/* EXWS_CS0 register configuration */
C_MEMIF_PAGE_MODE_DIS,C_MEMIF_PMS_4B,15,15,
/* DCCTRL_CS0 register configuration */
C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS
},
// CS4 - External SRAM
{
/* CONF_CS4 register configuration */
5,C_MEMIF_DVS_16,C_MEMIF_WRITE_EN,0,C_MEMIF_RODC_DIS,C_MEMIF_WRDC_DIS,C_MEMIF_WWS_VALUE_EN,
/* EXWS_CS4 register configuration */
C_MEMIF_PAGE_MODE_DIS,C_MEMIF_PMS_4B,15,15,
/* DCCTRL_CS4 register configuration */
C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS
},
// CS5 - FLASH
{
/* CONF_CS5 register configuration */
4,C_MEMIF_DVS_16,C_MEMIF_WRITE_EN,0,C_MEMIF_RODC_DIS,C_MEMIF_WRDC_DIS,C_MEMIF_WWS_VALUE_EN,
/* EXWS_CS5 register configuration */
C_MEMIF_PAGE_MODE_EN,C_MEMIF_PMS_16B,2,15,
/* DCCTRL_CS5 register configuration */
C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS
},
// BOARD == 45
#else
#error "This BOARD configuration is not supported"
#endif
};
/***************************************************************************
* C_CLOCK_CFG_156_78_52 configuration
**************************************************************************/
const T_DYNAMIC_CLOCK_CFG d_12_156_78_52_clock =
{
/* Index of the present clock configuration */
C_CLOCK_CFG_156_78_52,
/* DSP clock in kHz */
78000,
/* DPLL configuration */
DPLL_BYPASS_DIV_1, DPLL_LOCK_DIV_1, 12,
/* ARM clock configuration */
CLKM_SEL_DPLL, 3, CLKM_DISABLE_XP5,
/* DSP configuration */
CLKM_DSP_DIV_2,
/* DSP latencies configuration */
D_LAT_MCU_HOM2SAM,
D_LAT_MCU_BRIDGE,
D_LAT_MCU_BEF_FAST_ACCESS,
D_LAT_DSP_AFTER_SAM,
D_TRANSFER_RATE,
/* API-RHEA configuration */
/* API_WS */
1, 2,
// 1 WS in HOM mode to workaround HW bug 3504
// dma_arbtrs > Concurrent access to API from DMA and MCU
/* RHEA Access Factor */
// should be 0xFE00 due to no DMA limitation at 34MHz
// Must be updated according to ARM clock configuration
// Timeout must be set to 0xFF for chipset
// Calypso C035 at 52MHz
0, 0,
/* RHEA Timeout */
0xFF,
/* EMIF configuration */
/* structure used for CHIPSET 12 is different, see definition in sys_memif.h */
/* new memif drivers integrate new features as Page mode */
#if (BOARD == 6)
// CS0
{
/* CONF_CS0 register configuration */
5,C_MEMIF_DVS_16,C_MEMIF_WRITE_EN,0,C_MEMIF_RODC_DIS,C_MEMIF_WRDC_DIS,C_MEMIF_WWS_VALUE_EN,
/* EXWS_CS0 register configuration */
C_MEMIF_PAGE_MODE_DIS,C_MEMIF_PMS_4B,15,15,
/* DCCTRL_CS0 register configuration */
C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS
},
// CS4
{
/* CONF_CS4 register configuration */
5,C_MEMIF_DVS_16,C_MEMIF_WRITE_EN,0,C_MEMIF_RODC_DIS,C_MEMIF_WRDC_DIS,C_MEMIF_WWS_VALUE_EN,
/* EXWS_CS4 register configuration */
C_MEMIF_PAGE_MODE_DIS,C_MEMIF_PMS_4B,15,15,
/* DCCTRL_CS4 register configuration */
C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS
},
// CS5
{
/* CONF_CS5 register configuration */
5,C_MEMIF_DVS_16,C_MEMIF_WRITE_EN,0,C_MEMIF_RODC_DIS,C_MEMIF_WRDC_DIS,C_MEMIF_WWS_VALUE_EN,
/* EXWS_CS5 register configuration */
C_MEMIF_PAGE_MODE_DIS,C_MEMIF_PMS_4B,15,15,
/* DCCTRL_CS5 register configuration */
C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS
},
// BOARD == 6
#elif (BOARD == 42) // E-Sample SRAM
// CS0
{
/* CONF_CS0 register configuration */
4,C_MEMIF_DVS_16,C_MEMIF_WRITE_EN,0,C_MEMIF_RODC_DIS,C_MEMIF_WRDC_DIS,C_MEMIF_WWS_VALUE_EN,
/* EXWS_CS0 register configuration */
C_MEMIF_PAGE_MODE_DIS,C_MEMIF_PMS_4B,15,15,
/* DCCTRL_CS0 register configuration */
C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS
},
// CS4 - FLASH
{
/* CONF_CS4 register configuration */
4,C_MEMIF_DVS_16,C_MEMIF_WRITE_EN,0,C_MEMIF_RODC_DIS,C_MEMIF_WRDC_DIS,C_MEMIF_WWS_VALUE_EN,
/* EXWS_CS4 register configuration */
C_MEMIF_PAGE_MODE_DIS,C_MEMIF_PMS_4B,15,15,
/* DCCTRL_CS4 register configuration */
C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS
},
// CS5 - External SRAM
{
/* CONF_CS5 register configuration */
4,C_MEMIF_DVS_16,C_MEMIF_WRITE_EN,0,C_MEMIF_RODC_DIS,C_MEMIF_WRDC_DIS,C_MEMIF_WWS_VALUE_EN,
/* EXWS_CS5 register configuration */
C_MEMIF_PAGE_MODE_DIS,C_MEMIF_PMS_4B,15,15,
/* DCCTRL_CS5 register configuration */
C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS
},
// BOARD == 42
#elif (BOARD == 43) // E-Sample FLASH
// CS0
{
/* CONF_CS0 register configuration */
4,C_MEMIF_DVS_16,C_MEMIF_WRITE_EN,0,C_MEMIF_RODC_DIS,C_MEMIF_WRDC_DIS,C_MEMIF_WWS_VALUE_EN,
/* EXWS_CS0 register configuration */
C_MEMIF_PAGE_MODE_DIS,C_MEMIF_PMS_4B,15,15,
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