dynamic_clock_4.h

MMI层OBJ不能完全编译

 /************* Revision Controle System Header *************
 *                  GSM Layer 1 software
 * DYNAMIC_CLOCK_4_H
 *
 *        Filename dynamic_clock_4.h
 *  Copyright 2003 (C) Texas Instruments  
 *
 ************* Revision Controle System Header *************/

/***********************************************************************************************
 *          Only SAMSON/CALYPSO families are considered for dynamic clock configuration.
 ***********************************************************************************************
 *
 *                         CHIPSET = 4 (SAMSON)                            
 *
 ***********************************************************************************************
 *                         Supported clock configuration
 *
 *
 *       CHIPSET                78/78/13    78/78/39   104/104/52    156/78/52   130/130/65
 *                                 (0)         (1)          (2)         (3)         (4)
 *
 *  SAMSON C07            (4)      X            ?           NA          NA          NA
 *
 *
 *           BOARD                CHIPSET                         Access Time (ns)
 *                                                     CS0    CS1    CS2    CS3    CS4    CS5
 *  
 *    EVA4 (RAM)        (6)       SAMSON               100    NA     NA     NA     100    NA
 *    B-Sample          (7)       SAMSON
 *    C-Sample (RAM)    (8)       SAMSON               100    100    NA                   NA    (RD108, RD308) FLASH : AM29DL322T-70 (AMD) - SRAM : IC806 ????
 *    C-Sample (FLASH)  (9)       SAMSON               100    100    NA                   NA    (RD108, RD308) FLASH : AM29DL322T-70 (AMD) - SRAM : IC806 ????
 *    D-Sample (RAM)    (40)      SAMSON               85     70     70                   NA    (RD316, RD112) FLASH/SRAM : 28F640W30B70 (Intel) - SRAM : K1S321615M-EE10 (Samsung)
 *    D-Sample (FLASH)  (41)      SAMSON               70     70     85                   NA    (RD316, RD112) FLASH/SRAM : 28F640W30B70 (Intel) - SRAM : K1S321615M-EE10 (Samsung)
 *
 ***********************************************************************************************/

#include "chipset.cfg"
#include "board.cfg"

#if (CHIPSET == 4)
  
  #ifndef _DYNAMIC_CLOCK_4_H_
    #define _DYNAMIC_CLOCK_4_H_
  
    #ifdef _DYNAMIC_CLOCK_C_

     /***************************************************************************
     *                      C_CLOCK_CFG_78_78_13 configuration
     **************************************************************************/

    const T_DYNAMIC_CLOCK_CFG d_4_78_78_13_clock = 
        {
          /* Index of the present clock configuration */
          C_CLOCK_CFG_78_78_13,
  
          /* DSP clock in kHz */
          78000,
          
          /* DPLL configuration */
          DPLL_BYPASS_DIV_1, DPLL_LOCK_DIV_1, 6,

          /* ARM clock configuration */
          CLKM_SEL_DPLL, 6, CLKM_DISABLE_XP5,

          /* DSP latencies configuration */
          D_LAT_MCU_HOM2SAM,
          D_LAT_MCU_BRIDGE,
          D_LAT_MCU_BEF_FAST_ACCESS,
          D_LAT_DSP_AFTER_SAM,
          D_TRANSFER_RATE,

          /* API-RHEA configuration */
          /* API_WS */
          0, 0,
          /* RHEA Access Factor */
          0, 0,
          /* RHEA Timeout */
          0x7F,

          /* EMIF configuration */
          #if (BOARD == 6)
            { 0, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS0
            { 0, MEM_DVS_8,  MEM_WRITE_EN, 0 }, // CS1
            { 1, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS2
            { 5, MEM_DVS_8,  MEM_WRITE_EN, 0 }, // CS3
            { 0, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS4
          #elif (BOARD == 7)
            { 1, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS0
            { 0, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS1
            { 0, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS2
            { 5, MEM_DVS_8,  MEM_WRITE_EN, 0 }, // CS3
            { 0, MEM_DVS_8,  MEM_WRITE_EN, 0 }, // CS4
          #elif (BOARD == 8)
            { 0, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS0
            { 1, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS1
            { 1, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS2
            { 5, MEM_DVS_8,  MEM_WRITE_EN, 0 }, // CS3
            { 0, MEM_DVS_8,  MEM_WRITE_EN, 0 }, // CS4
          #elif (BOARD == 9)
            { 1, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS0
            { 0, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS1
            { 1, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS2
            { 5, MEM_DVS_8,  MEM_WRITE_EN, 0 }, // CS3
            { 0, MEM_DVS_8,  MEM_WRITE_EN, 0 }, // CS4
          #elif (BOARD == 40)
            { 0, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS0
            { 1, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS1
            { 1, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS2
            { 5, MEM_DVS_8,  MEM_WRITE_EN, 0 }, // CS3
            { 0, MEM_DVS_8,  MEM_WRITE_EN, 0 }, // CS4
          #elif (BOARD == 41)
            { 1, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS0
            { 0, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS1
            { 1, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS2
            { 5, MEM_DVS_8,  MEM_WRITE_EN, 0 }, // CS3
            { 0, MEM_DVS_8,  MEM_WRITE_EN, 0 }, // CS4
          #else
            #error "This BOARD configuration is not supported"
          #endif

          { 0, MEM_DVS_32, MEM_WRITE_EN, 0 },   // CS6
          { 0, MEM_DVS_32, MEM_WRITE_EN, 0 },   // CS7

        };

     /***************************************************************************
      *                     C_CLOCK_CFG_78_78_39 configuration
      **************************************************************************/
    /* Not Applicable */

    const T_DYNAMIC_CLOCK_CFG * a_dynamic_clock_cfg[C_NB_MAX_CLOCK_CONFIG] = {
            &d_4_78_78_13_clock,            /* 78/78/13 MHz */
            (T_DYNAMIC_CLOCK_CFG *) NULL,
          };

    #else
      extern const T_DYNAMIC_CLOCK_CFG * a_dynamic_clock_cfg[C_NB_MAX_CLOCK_CONFIG];
    #endif  /* _DYNAMIC_CLOCK_C_ */

  #endif  /* _DYNAMIC_CLOCK_4_H_ */

#endif   /* CHIPSET == 4 */