📄 init.c
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// AI_EnableBit (2);
AI_ConfigBitAsInput (11);
AI_EnableBit (11);
AI_ConfigBitAsOutput (13);
AI_EnableBit (13);
AI_Power (1); /* Maintain power supply. */
#elif (BOARD == 6) || (BOARD == 7) || (BOARD == 8) || (BOARD == 9) || \
(BOARD == 40) || (BOARD == 41) || (BOARD == 42) || (BOARD == 43) || (BOARD == 45) || \
(BOARD == 35) || (BOARD == 46) || (BOARD == 70) || (BOARD == 71)
#if (PSP_STANDALONE == 0)
// RIF/SPI rising edge clock for ULYSSE
//--------------------------------------------------
#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)|| (ANLG_FAM == 11))
#if ((CHIPSET >= 3))
#if (CHIPSET == 12)
F_CONF_RIF_RX_RISING_EDGE;
F_CONF_SPI_RX_RISING_EDGE;
#elif (CHIPSET == 15)
//do the DRP init here for Locosto
#if (L1_DRP == 1)
// drp_power_on(); This should be done after the script is downloaded.
#endif
#else
#if (BOARD==35)
*((volatile SYS_UWORD16 *) ASIC_CONF) = 0x2000;
#else
*((volatile SYS_UWORD16 *) ASIC_CONF) = 0x6000;
#endif /* (BOARD == 35) */
#endif
#endif
#endif /* ANLG(ANALOG)) */
#if (OP_L1_STANDALONE == 1)
#if (BOARD == 40) || (BOARD == 41) || \
(BOARD == 42) || (BOARD == 43) || (BOARD == 45)
// enable 8 Ohm amplifier for audio on D-sample
AI_ConfigBitAsOutput (1);
AI_SetBit(1);
#elif (BOARD == 70) || (BOARD == 71)
//Locosto I-sample or UPP costo board.BOARD
// Initialize the ARMIO bits as per the I-sample spec
// FIXME
#endif
#endif /* (OP_L1_STANDALONE == 1) */
#endif /* PSP_STANDALONE ==0 */
// Watchdog
//--------------------------------------------------
TM_DisableWatchdog(); /* Disable Watchdog */
#if (CHIPSET == 12) || (CHIPSET == 15)
TM_SEC_DisableWatchdog();
#endif
#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15))
#if (CHIPSET == 12)
#if 0 /* example of configuration for DMA debug */
#if (BOARD == 6) /* debug on EVA 4 , GPO2 must not be changed */
/* TPU_FRAME, NMIIT, IACKn */
F_DBG_IRQ_CONFIG(C_DBG_IRQ_IRQ4|C_DBG_IRQ_NMIIT|C_DBG_IRQ_IACKN);
/* NDMA_REQ_VIEW1, NDMA_REQ_VIEW0, DMA_V(1), DMA_S(1), DMAREQ_P1(3:0)*/
F_DBG_DMA_P1_NDFLASH_CONFIG(C_DBG_DMA_P1_NDFLASH_NDMA_REQ_VIEW_1 |
C_DBG_DMA_P1_NDFLASH_NDMA_REQ_VIEW_0 |
C_DBG_DMA_P1_NDFLASH_DMA_REQ_P1_3 |
C_DBG_DMA_P1_NDFLASH_DMA_REQ_P1_2 |
C_DBG_DMA_P1_NDFLASH_DMA_REQ_P1_1 |
C_DBG_DMA_P1_NDFLASH_DMA_REQ_P1_0 |
C_DBG_DMA_P1_NDFLASH_DMA_REQ_S_1 |
C_DBG_DMA_P1_NDFLASH_DMA_REQ_V1 );
/* DMA_REQ_S(2)*/
F_DBG_DMA_P2_CONFIG(C_DBG_DMA_P2_DMA_REQ_S2);
/* DMA_CLK_REQ, BRIDGE_CLK */
F_DBG_CLK1_CONFIG(C_DBG_CLK1_DMA_CLK_REQ |
C_DBG_CLK1_BRIDGE_CLK );
/* XIO_nREADY */
F_DBG_IMIF_CONFIG(C_DBG_IMIF_XIO_NREADY_MEM);
/* DSP_nIRQ_VIEW1, DSP_nIRQ_VIEW0, BRIDGE_EN */
F_DBG_KB_USIM_SHD_CONFIG(C_DBG_KB_USIM_SHD_DSP_NIRQ_VIEW_1 |
C_DBG_KB_USIM_SHD_DSP_NIRQ_VIEW_0 |
C_DBG_KB_USIM_SHD_BRIDGE_EN );
/* RHEA_nREADY , RHEA_nSTROBE */
F_DBG_USIM_CONFIG(C_DBG_USIM_RHEA_NSTROBE |
C_DBG_USIM_RHEA_NREADY );
/* XIO_STROBE */
F_DBG_MISC2_CONFIG(C_DBG_MISC2_X_IOSTRBN);
/* DMA_CLK_REQ */
F_DBG_CLK2_CONFIG(C_DBG_CLK2_DMA_CLK_REQ2);
/* DSP_IRQ_SEL0=DMA, DSP_IRQ_SEL1=DMA, DMA_REQ_SEL0=RIF_RX, DMA_REQ_SEL1=RIF_RX */
F_DBG_VIEW_CONFIG(0,0,C_DBG_DSP_INT_DMA,
C_DBG_DSP_INT_DMA,
C_DMA_CHANNEL_RIF_RX,
C_DMA_CHANNEL_RIF_RX);
#endif /* (BOARD == 6) */
#endif /* DMA debug example */
#else
/*
* Configure ASIC in order to output the DPLL and ARM clock
*/
// (*( volatile UWORD16* )(0xFFFEF008)) = 0x8000; // DPLL
// (*( volatile UWORD16* )(0xFFFEF00E)) = 0x0004; // ARM clock
// (*( volatile UWORD16* )(0xfffef004)) = 0x0600; // DSP clock + nIACK
#endif /* (CHIPSET == 12) || CHIPSET == 15*/
/*
* Enable/Disable of clock switch off for INTH, TIMER, BRIDGE and DPLL modules
*/
// IRQ, Timer and bridge may SLEEP
// In first step, same configuration as SAMSON
//--------------------------------------------------
#if (CHIPSET == 12)
CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_TIMER_DIS | CLKM_BRIDGE_DIS | CLKM_DPLL_DIS);
#elif (CHIPSET == 15)
CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_TIMER_DIS | CLKM_CPORT_EN | CLKM_BRIDGE_DIS | 0x8000 ); /* CLKM_DPLL_DIS is remove by Ranga*/
#else
CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_TIMER_DIS);
// Select VTCXO input frequency
//--------------------------------------------------
CLKM_UNUSED_VTCXO_26MHZ;
// Rita RF uses 26MHz VCXO
#if (RF_FAM == 12)
CLKM_USE_VTCXO_26MHZ;
#endif
// Renesas RF uses 26MHz on F-sample but 13MHz on TEB
#if (RF_FAM == 43) && (BOARD == 46)
CLKM_USE_VTCXO_26MHZ;
#endif
#endif
#if (CHIPSET ==15)
//Enable APLL
*((volatile unsigned short *) (C_MAP_CLKM_BASE+0x10)) = 0x01|0x6;
// UART Clock from APLL
*((volatile unsigned short *) CLKM_CNTL_CLK_PROG_FREE_RUNN) = 0x0001;
#endif
//
// Control HOM/SAM automatic switching
//--------------------------------------------------
*((volatile unsigned short *) CLKM_CNTL_CLK) &= ~CLKM_EN_IDLE3_FLG;
/*
* Disable and Clear all pending interrupts
*/
#if (CHIPSET == 12) || (CHIPSET == 15)
F_INTH_DISABLE_ALL_IT; // MASK all it
F_INTH2_VALID_NEXT(C_INTH_IRQ); // reset current IT in INTH2 IRQ
F_INTH_VALID_NEXT(C_INTH_IRQ); // reset current IT in INTH IRQ
F_INTH_VALID_NEXT(C_INTH_FIQ); // reset current IT in INTH FIQ
F_INTH_RESET_ALL_IT; // reset all IRQ/FIQ source
#else
INTH_DISABLEALLIT;
INTH_RESETALLIT;
INTH_CLEAR; /* reset IRQ/FIQ source */
#endif
#if (CHIPSET == 12)
/* API-RHEA control register configuration */
f_memif_init_api_rhea_ctrl(C_MEMIF_API_RHEA_ADAPT,
C_MEMIF_API_RHEA_ADAPT,
C_MEMIF_API_RHEA_ADAPT,
C_MEMIF_API_RHEA_NO_DEBUG);
#if ((BOARD == 43) || (BOARD == 45))
// if Esample,Evaconso active extended page mode
// With Calypso+ chipset, extended page mode can be enabled
// only if W_A_CALYPSO_PLUS_SPR_19599 is set to one in l1_confg.h.
// see L1_MCU-SPR-17515 and L1_MCU-SPR-19599 for more information
f_memif_extended_page_mode_enable();
#endif
#endif /* (CHIPSET == 12) */
#if (CHIPSET == 15)
/* API-RHEA control register configuration */
#if 0 //fangcj add for debug: need to be removed
f_emif_api_rhea_conf(C_RHEA_STROBE0_ACCESS_SIZE_ADAPT_ENABLE,
C_RHEA_STROBE1_ACCESS_SIZE_ADAPT_ENABLE,
C_API_ACCESS_SIZE_ADAPT_ENABLE,
C_ARM_DEBUG_DISABLE);
#else
f_emif_api_rhea_conf(C_RHEA_STROBE0_ACCESS_SIZE_ADAPT_ENABLE,
C_RHEA_STROBE1_ACCESS_SIZE_ADAPT_ENABLE,
C_API_ACCESS_SIZE_ADAPT_ENABLE,
C_ARM_DEBUG_ENABLE);
#endif
#if (BOARD == 70) || (BOARD == 71)
// set the EMIF settings here for locosto
// We could have the default settings here and
// then change it after dynamic clock config
/* MCP RAM Setting Is being done here */
#if 0 /* This is commented out by Ranga */
#if (PSP_FAILSAFE!=1)
bcrTmpVal = *((volatile unsigned char *)0x007FFFFFE);
bcrTmpVal +=1;
bcrTmpVal = *((volatile unsigned char *)0x007FFFFFE);
*((volatile unsigned char *)0x007FFFFFE)=0x0001;
*((volatile unsigned char *)0x007FFFFFE)=0x1542;
/* Setting NOR Flash to these 3 Wait State */
*((volatile char *)0x06000AAA)=0xAA;
*((volatile char *)0x06000555)=0x55;
*((volatile char *)0x06016AAA)=0xC0;
#endif
#endif
#endif
#endif /* (CHIPSET == 15) */
/*
* Initialize current DSP clock to 0 in order to pass through
* the right DSP latency configuration (increase DSP clock)
* in f_dynamic_clock_cfg().
* Obviously, the real DSP clock is not 0kHz.
* d_dsp_cur_clk will be updated after clock configuration in f_dynamic_clock_cfg().
*/
d_dsp_cur_clk = 0; // Used to keep track of current DSP clock.
/* Dynamic clock configuration */
f_dynamic_clock_cfg(C_CLOCK_CFG_DEFAULT);
// Write_en_0 = 0 , Write_en_1 = 0
RHEA_INITARM(0,0);
#if (CHIPSET ==15)
// Mark USB on 52 MHZ Clock
*((volatile unsigned short *) (CLKM_CNTL_CLK_USB)) = 0x02;
#endif
#if (CHIPSET == 12) || ((CHIPSET == 10) && (OP_WCP == 1))
/* Allocate the 0.5 Mbits Shared RAM to the DSP */
f_memif_shared_sram_allocation(C_MEMIF_DSPMS_0_5MBITS_TO_DSP);
#endif
// INTH
//--------------------------------------------------
#if (CHIPSET == 12) || (CHIPSET == 15)
#if (GSM_IDLE_RAM != 0)
f_inth_setup((T_INTH_CONFIG *)a_inth_config_idle_ram); // setup configuration IT handlers
#else
f_inth_setup((T_INTH_CONFIG *)a_inth_config); // setup configuration IT handlers
#endif
#else
IQ_SetupInterrupts();
#endif
#if (CHIPSET == 12) || (CHIPSET == 15)
#ifdef SYS_DMA
f_dma_global_parameter_set((T_DMA_TYPE_GLOBAL_PARAMETER *)&d_dma_global_parameter);
//allocate channel 0 to DSP
f_dma_channel_allocation_set(C_DMA_CHANNEL_0, C_DMA_CHANNEL_DSP);
#else
f_dma_global_parameter_set((T_DMA_TYPE_GLOBAL_PARAMETER *)&d_dma_global_parameter);
//allocate channel 0 to DSP
C_DMA_CAR_REG |= (C_DMA_CHANNEL_DSP << C_DMA_CHANNEL_0);
#endif
#else
// DMA
//--------------------------------------------------
// channel0 = Arm, channel1 = Lead, channel2 = forced to Arm, channel3=forced to Arm, dma_burst = 0001, priority = same
#ifdef SYS_DMA
DMA_ALLOCDMA(1,0,1,1); // Channel 1 used by DSP with RIF RX
#endif
#endif
/* CHIPSET = 4 or 7 or 8 or 10 or 11 or 12 */
#else
// RHEA Bridge
//--------------------------------------------------
// ACCES_FAC_0 = 0, ACCES_FAC_1 = 0 ,TIMEOUT = 0x7F
RHEA_INITRHEA(0,0,0x7F);
#if (CHIPSET == 6)
// WS_H = 1 , WS_L = 15
RHEA_INITAPI(1,15); // should be 0x01E1 for 65 Mhz
#else
// WS_H = 0 , WS_L = 7
RHEA_INITAPI(0,7); // should be 0x0101 for 65 Mhz
#endif
// Write_en_0 = 0 , Write_en_1 = 0
RHEA_INITARM(0,0);
// INTH
//--------------------------------------------------
INTH_DISABLEALLIT; // MASK all it
INTH_CLEAR; // reset IRQ/FIQ source
IQ_SetupInterrupts();
// DMA
//--------------------------------------------------
// channel0 = Arm, channel1 = Lead, dma_burst = 0001, priority = same
#ifdef SYS_DMA
DMA_ALLOCDMA(1,0,1,1); // should be 0x25 (channel 1 = lead)
#endif
#if (CHIPSET == 6)
// Memory WS configuration for ULYSS/G1 (26 Mhz) board
//-----------------------------------------------------
MEM_INIT_CS2(2,MEM_DVS_16,MEM_WRITE_EN,0);
#endif
// CLKM
//--------------------------------------------------
CLKM_InitARMClock(0x00, 2); /* no low freq, no ext clock, div by 1 */
#if (CHIPSET == 6)
CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS | CLKM_VTCXO_26);
#else
CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS);
#endif
#endif /* CHIPSET = 4 or 7 or 8 or 10 or 11 or 12 */
// Freeze ULPD timer ....
//--------------------------------------------------
*((volatile SYS_UWORD16 *) ULDP_GSM_TIMER_INIT_REG ) = 0;
*((volatile SYS_UWORD16 *) ULDP_GSM_TIMER_CTRL_REG ) = TPU_FREEZE;
// reset INC_SIXTEEN and INC_FRAC
//--------------------------------------------------
#if (OP_L1_STANDALONE == 1)
l1ctl_pgm_clk32(DEFAULT_HFMHZ_VALUE,DEFAULT_32KHZ_VALUE);
#else
ULDP_INCSIXTEEN_UPDATE(132); //32768.29038 =>132, 32500 => 133
// 26000 --> 166
ULDP_INCFRAC_UPDATE(15840); //32768.29038 =>15840, 32500 => 21845
// 26000 --> 43691
#endif /* OP_L1_STANDALONE */
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