📄 init.c
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#if GSM_IDLE_RAM_DEBUG
{ C_INTH_IRQ, C_INTH_LEVEL, 0x01, flash_access_handler }, // 21 : EXTERNAL IRQ 1
{ C_INTH_IRQ, C_INTH_LEVEL, 0x01, ext_ram_access_handler }, // 22 : EXTERNAL IRQ 2
#else
{ C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 21 : EXTERNAL IRQ 1
{ C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 22 : EXTERNAL IRQ 2
#endif
{ C_INTH_FIQ, C_INTH_LEVEL, 0xFF, ext_ram_fiq_inth_handler }, // 23 : USIM Card Detect
{ C_INTH_IRQ, C_INTH_EDGE, 0xFF, ext_ram_irq_inth_handler }, // 24 : USIM
{ C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 25 : LCD
#if (OP_L1_STANDALONE == 1)
{ C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 26 : USB
#else
{ C_INTH_IRQ, C_INTH_LEVEL, 0x00, ext_ram_irq_inth_handler }, // 26 : USB
#endif
#if (OP_L1_STANDALONE == 1)
{ C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 27 : MMC/SD/MS
#else
#ifdef RVM_MC_SWE
{ C_INTH_IRQ, C_INTH_LEVEL, 0x01, ext_ram_irq_inth_handler }, // 27 : MMC/SD/MS
#else
{ C_INTH_IRQ, C_INTH_EDGE, 0xFF, ext_ram_irq_inth_handler },
#endif
#endif
{ C_INTH_IRQ, C_INTH_LEVEL, 0x02, ext_ram_irq_inth_handler }, // 28 : UART_MODEM2
#if (OP_L1_STANDALONE == 1)
{ C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 29 : 2nd Interrupt Handler
#else
{ C_INTH_IRQ, C_INTH_LEVEL, 0x02, ext_ram_irq_inth_handler }, // 29 : 2nd Interrupt Handler
#endif
#if (OP_L1_STANDALONE == 1)
{ C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 30 : I2C
#else
{ C_INTH_IRQ, C_INTH_EDGE, 0x01, ext_ram_irq_inth_handler }, // 30 : I2C
#endif
#if (OP_L1_STANDALONE == 1)
{ C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 31 : NAND FLASH
#else
{ C_INTH_IRQ, C_INTH_EDGE, 0x02, ext_ram_irq_inth_handler }, // 31 : NAND FLASH
#endif
{ C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 0 : RNG
{ C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 1 : SHA1/MD5
{ C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 2 : EMPU
#if (OP_L1_STANDALONE == 1)
{ C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 3 : Secure DMA
#else
{ C_INTH_IRQ, C_INTH_LEVEL,?0x03,牋 ext_ram_irq_inth_handler? }, // 3?: Secure DMA
#endif
{ C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler } // 4 : Secure TIMER
};
#endif //(GSM_IDLE_RAM != 0)
#endif /* (CHIPSET ==12) */
#if (CHIPSET == 15)
const T_INTH_CONFIG a_inth_config[C_INTH_NB_INTERRUPT] =
{ // IRQ/FIQ LEVEL/EDGE PRIORITY HANDLER
{ C_INTH_IRQ, C_INTH_EDGE, 0x01, IQ_TimerHandler }, // 0 : WATCHDOG TIMER
{ C_INTH_IRQ, C_INTH_EDGE, 0x02, IQ_TimerHandler1 }, // 1 : TIMER 1
{ C_INTH_IRQ, C_INTH_EDGE, 0x02, IQ_TimerHandler2 }, // 2 : TIMER 2
{ C_INTH_FIQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 3 : MCSI
#if (PSP_STANDALONE == 0)
{ C_INTH_IRQ, C_INTH_EDGE, 0x00, IQ_FrameHandler }, // 4 : TPU FRAME
#else
{ C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 4 : TPU FRAME
#endif
{ C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 5 : TPU PAGE
#if (OP_L1_STANDALONE == 1)
{ C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 6 : DRP DBB
#else
{ C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 6 : DRP DBB
#endif
{ C_INTH_IRQ, C_INTH_LEVEL, 0x02, SER_uart_irda_handler }, // 7 : UART_IRDA
#if (OP_L1_STANDALONE == 1)
{ C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 8 : KEYBOARD
#else
{ C_INTH_IRQ, C_INTH_LEVEL, 0x01, IQ_KeypadHandler }, // 8 : KEYBOARD
#endif
{ C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 9 : DRP DBB RX
#ifdef RVM_CAMD_SWE
{ C_INTH_IRQ, C_INTH_LEVEL, 0x03, f_camera_interrupt_manager }, // 10 : CAMERA
#else
{ C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 10 : CAMERA
#endif
#if (PSP_STANDALONE == 0)
{ C_INTH_IRQ, C_INTH_EDGE, 0x00, IQ_Gauging_Handler }, // 11 : ULPD_GAUGING
#else
{ C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 11 : ULPD_GAUGING
#endif
{ C_INTH_IRQ, C_INTH_EDGE, 0x08, IQ_External }, // 12 : ABB_IRQ
{ C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 13 : MSSPI
#ifdef SYS_DMA
{ C_INTH_IRQ, C_INTH_LEVEL, 0x06, f_dma_interrupt_manager }, // 14 : DMA
#else
{ C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy },
#endif
#if (PSP_STANDALONE == 0)
{ C_INTH_IRQ, C_INTH_EDGE, 0x03, IQ_ApiHandler }, // 15 : API
#else
{ C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 15 : API
#endif
//revise by QiangZeng061027
// { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 16 : GPIO
//{ C_INTH_IRQ, C_INTH_EDGE, 0x03, IQ_Gpio1_Handle }, // 16 : GPIO
{ C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 16 : GPIO
{ C_INTH_IRQ, C_INTH_EDGE, 0x03, f_inth_uart_wakeup }, // SER_uart_irda_handler17 : ABB_FIQ
{ C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 18 : DRP DBB RX
#if (PSP_STANDALONE == 0)
{ C_INTH_IRQ, C_INTH_LEVEL, 0x03, IQ_GsmTim_Handler }, // 19 : ULPD GSM TIMER
#else
{ C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 19 : ULPD GSM TIMER
#endif
{ C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 20 : GEA
#if GSM_IDLE_RAM_DEBUG
{ C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 21 : GPIO1
{ C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 22 : GPIO2
#else
// { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 21 : GPIO1
{ C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 21 : GPIO1
// { C_INTH_IRQ, C_INTH_EDGE, 0x01, IQ_Gpio1_Handle }, // 21 : GPIO1
{ C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 22 : GPIO2
// { C_INTH_IRQ, C_INTH_EDGE, 0x01, IQ_Gpio2_Handle }, // 21 : GPIO1
#endif
{ C_INTH_FIQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 23 : CPORT
#if(OP_L1_STANDALONE == 1)
{ C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 24 : USIM
#else
{ C_INTH_IRQ, C_INTH_EDGE, 0x04, bspUicc_Phy_intCHandler }, // 24 : USIM
#endif
{ C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 25 : LCD
#if (OP_L1_STANDALONE == 1)
{ C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 26 : USB
#else
#ifdef RVM_USB_SWE
{ C_INTH_IRQ, C_INTH_LEVEL, 0x03, usb_int_handler }, // 26 : USB
#else
{ C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy },
#endif
#endif
{ C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 27 : not used
{ C_INTH_IRQ, C_INTH_LEVEL, 0x03, bspI2c_Handeler2 }, // 28 : I2C TRITON
{ C_INTH_IRQ, C_INTH_LEVEL, 0x02, f_inth_2nd_level_handler }, // 29 : 2nd Interrupt Handler
{ C_INTH_IRQ, C_INTH_LEVEL, 0x03, bspI2c_Handeler1 }, // 30 : I2C
#if (OP_L1_STANDALONE == 1)
{ C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 31 : NAND FLASH
#else
#ifdef RVM_NAN_SWE
{ C_INTH_IRQ, C_INTH_LEVEL, 0x02, nan_bm_IT_handler }, // 31 : NAND FLASH
#else
{ C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy },
#endif
#endif
{ C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 0 : RNG
{ C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 1 : SHA1/MD5
{ C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 2 : EMPU
#ifdef SYS_DMA
{ C_INTH_IRQ, C_INTH_LEVEL, 0x06, f_dma_interrupt_manager }, // 14 : DMA
#else
{ C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy },
#endif
{ C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy } // 4 : Secure TIMER
};
#endif /* CHIPSET == 15 */
#pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_END
#endif // !((MOVE_IN_INTERNAL_RAM == 1) && (GSM_IDLE_RAM !=0))
#if (CHIPSET == 12)
const T_DMA_TYPE_GLOBAL_PARAMETER d_dma_global_parameter=
{
#if (CHIPSET_PG == CP_PG_F751685A)
C_DMA_AUTO_GATE_ON,
#else
C_DMA_AUTO_GATE_OFF,
#endif /* endif (CHIPSET_PG == F751685A) */
C_DMA_API_PRIO_ARM,
C_DMA_RHEA_PRIO_ARM,
C_DMA_IMIF_PRIO_CPU_4
};
#endif /* (CHIPSET ==12) */
#if (CHIPSET == 15)
const T_DMA_TYPE_GLOBAL_PARAMETER d_dma_global_parameter=
{
C_DMA_AUTO_GATE_ON,
C_DMA_API_PRIO_ARM,
C_DMA_RHEA_PRIO_ARM,
C_DMA_IMIF_PRIO_CPU_4,
C_DMA_IPERIF_PRIO_CPU_4, // set same as the IMIF priority. Actual value need to decided
C_DMA_EMIF_DMA_PRIO_7, // Actual value need to be decided
C_DMA_EMIF_MCU_PRIO_5 // Actual value need to be decided
};
#endif
#if (GSM_IDLE_RAM != 0)
#define IRQ_STACK_SIZE 128
#pragma DATA_SECTION(irq_stack,".irqstk");
UWORD32 irq_stack[IRQ_STACK_SIZE/4];
const UWORD32 irq_stack_size = IRQ_STACK_SIZE;
#define FIQ_STACK_SIZE 512
#pragma DATA_SECTION(fiq_stack,".fiqstk");
UWORD32 fiq_stack[FIQ_STACK_SIZE/4];
const UWORD32 fiq_stack_size = FIQ_STACK_SIZE;
#define SVC_STACK_SIZE 1024
#pragma DATA_SECTION(svc_stack,".svcstk");
UWORD32 svc_stack[SVC_STACK_SIZE/4];
const UWORD32 svc_stack_size = SVC_STACK_SIZE;
#define TIMER_HISR_STACK_SIZE 1024
#pragma DATA_SECTION(timer_hisr_stack,".timstk");
UWORD32 timer_hisr_stack[TIMER_HISR_STACK_SIZE/4];
const UWORD32 timer_hisr_stack_size = TIMER_HISR_STACK_SIZE;
#endif
/* HISR_STACK_SHARING: Create global stacks to be used by all HISRs
* having the same priority */
#if (CODE_VERSION != SIMULATION)
#ifndef SYS_DMA
void f_dma_global_parameter_set(T_DMA_TYPE_GLOBAL_PARAMETER *p_dma_global_parameter)
{
if (p_dma_global_parameter->d_dma_global_auto_gate==C_DMA_AUTO_GATE_ON)
{
C_DMA_GCR_REG |= (C_DMA_AUTO_GATE_ON << C_DMA_GCR_AUTO_GATE_POS );
}
else
{
C_DMA_GCR_REG &= ~( C_DMA_GCR_AUTO_GATE_MASK << C_DMA_GCR_AUTO_GATE_POS );
}
C_DMA_AR_REG = (
(p_dma_global_parameter->d_dma_global_api_prio << C_DMA_AR_API_PRIO_POS)
| (p_dma_global_parameter->d_dma_global_rhea_prio << C_DMA_AR_RHEA_PRIO_POS)
| (p_dma_global_parameter->d_dma_global_imif_prio << C_DMA_AR_IMIF_PRIO_POS)
#if (CHIPSET == 15)
| (p_dma_global_parameter->d_dma_global_iperif_prio << C_DMA_AR_IPERIF_PRIO_POS)
#endif
);
#if (CHIPSET == 15)
f_emif_set_priority(p_dma_global_parameter->d_dma_global_emif_dma_prio,
p_dma_global_parameter->d_dma_global_emif_mcu_prio);
#if 0
C_EMIF_LRU_PRIORITY_REG = (
(p_dma_global_parameter->d_dma_global_emif_dma_prio << C_EMIF_DMA_POS)
| (p_dma_global_parameter->d_dma_global_emif_mcu_prio << C_EMIF_MPU_POS)
);
#endif
#endif
} /*f_dma_global_parameter_set() */
#endif
#ifndef RVM_USB_SWE
void Init_USB_Sleep_Enable()
{
(*(volatile Uint16 *) 0xFFFFB00C) = 0x102; // USB SYSCON1: disable power-off circuitry and lock configuration
}
#endif
/*
* Init_Target
*
* Performs low-level HW Initialization.
*/
void Init_Target(void)
{
unsigned long armio_io_cntl;
#if (BOARD==70)|| (BOARD==71)
/* Variable for reading the BCR for MCP RAM */
unsigned short bcrTmpVal;
#endif
#if (CHIPSET == 15)
char detect_code[80];
typedef void (*pf_t)(UWORD32, UWORD16 *, UWORD16 *);
extern void ffsdrv_device_id_read(UWORD32 base_addr, UWORD16 *manufact, UWORD16 *device);
pf_t myfp;
UWORD16 manufact;
UWORD16 device_id[3];
#endif
#if (BOARD == 5)
#define WS_ROM (1)
#define WS_RAM (1)
#define WS_APIF (1)
#define WS_CS2 (7) /* LCD on EVA3. */
#define WS_CS0 (7) /* DUART on EVA3. UART16750 and latch on A-Sample. */
#define WS_CS1 (7) /* LCD on A-Sample. */
IQ_InitWaitState (WS_ROM, WS_RAM, WS_APIF, WS_CS2, WS_CS0, WS_CS1);
IQ_InitClock (2); /* Internal clock division factor. */
IQ_MaskAll (); /* Mask all interrupts. */
IQ_SetupInterrupts (); /* IRQ priorities. */
TM_DisableWatchdog ();
/*
* Reset all TSP and DBG fdefault values
*/
AI_ResetTspIO ();
AI_ResetDbgReg ();
AI_ResetIoConfig ();
/*
* Warning! The external reset signal is connected to the Omega and the
* external device. If the layer 1 is used its initialization removes
* the external reset. If the application does not use the layer 1
* you must remove the external reset (bit 2 of the reset control
* register 0x505808).
*/
AI_ResetTspIO();
AI_ResetDbgReg();
AI_ResetIoConfig();
/*
* Configure all IOs (see RD300 specification).
*/
AI_ConfigBitAsInput (1);
AI_EnableBit (1);
// AI_ConfigBitAsOutput (2);
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