asm_defs.inc

MMI层OBJ不能完全编译

;INT_NUM_PRIOR_REGS      .equ    22          ; Number of Interrupt Priority Registers

;INTERRUPT_MODE          .equ    0x0000      ; Sets the interrupt mode to IRQ
;INTERRUPTS_DISABLE      .equ    0xFFFF      ; Make sure all interrupts are disabled

;INT_EN_TIMER            .equ    0x01        ; Enables Timer 0
;IRQ_ENTRY               .equ    0x02        ; Set interrupts to IRQ

;INT_NO_PENDING          .equ    0x0         ; Value returned by offset register for no pending
                                            ; interrupts
;MASK_REG_SPACE          .equ    8

;MASK1_STACK_OFFSET      .equ    24          ; Level 1 mask register
;MASK2_STACK_OFFSET      .equ    28          ; Level 2 mask register
;MASK3_STACK_OFFSET      .equ    32          ; Level 3 mask register

;MASK_REG1_VECT          .equ    32          ; Max vector number (combining interrupt bank 0 and 1
                                            ; registers)

;INTERRUPTS_ADDR         .equ    0x00000000  ; Begining address for all handlers


;***********************************
;* TARGET INITIALIZATION CONSTANTS *
;***********************************

;EMI_BASE                .equ    0x00030A00  ; External memory interface base address
;CS0_CNTL1               .equ    0x00        ; Chip select 0 control 1 offset
;CS0_CNTL2               .equ    0x02        ; Chip select 0 control 2 offset
;CS1_CNTL1A              .equ    0x04        ; Chip select 1 control 1A offset
;CS1_CNTL1B              .equ    0x06        ; Chip select 1 control 1B offset
;CS1_CNTL2               .equ    0x08        ; Chip select 1 control 2 offset
;CS2_CNTL1               .equ    0x0A        ; Chip select 2 control 1 offset
;CS2_CNTL2               .equ    0x0C        ; Chip select 2 control 2 offset
;CS3_CNTL1               .equ    0x0E        ; Chip select 3 control 1 offset
;CS3_CNTL2               .equ    0x10        ; Chip select 3 control 2 offset
;CS4_CNTL1               .equ    0x12        ; Chip select 4 control 1 offset
;CS4_CNTL2               .equ    0x14        ; Chip select 4 control 2 offset

;CS0_CNTL1_BITS          .equ    0x4455      ; Bits for chip select 0 control 1 register
;CS0_CNTL2_BITS          .equ    0x0012      ; Bits for chip select 0 control 2 register
;CS1_CNTL1A_BITS         .equ    0x1E1F      ; Bits for chip select 1 control 1A register
;CS1_CNTL1B_BITS         .equ    0x1D1D      ; Bits for chip select 1 control 1B register
;CS3_CNTL1_BITS          .equ    0x5557      ; Bits for chip select 3 control 1 register
;CS3_CNTL2_BITS          .equ    0x1222      ; Bits for chip select 3 control 2 register
;CS4_CNTL1_BITS          .equ    0xCFFF      ; Bits for chip select 3 control 1 register
;CS4_CNTL2_BITS          .equ    0x7330      ; Bits for chip select 4 control 2 register

; Defines for the SDRAM Controller

;SDRAM_BASE              .equ    0x00030980  ; SDRAM Controller Base Address
;SDRAM_SDMODE            .equ    0x26        ; SDRAM SDMODE offset
;SDRAM_REFCTL            .equ    0x28        ; SDRAM Refresh Control offset
;SDRAM_PRTYON            .equ    0x4E        ; SDRAM Priority ON/OFF offset
;SDRAM_SDPRY1            .equ    0x3A        ; SDRAM Priority 1 offset
;SDRAM_SDPRY2            .equ    0x3C        ; SDRAM Priority 2 offset
;SDRAM_SDPRY3            .equ    0x3E        ; SDRAM Priority 3 offset
;SDRAM_SDPRY4            .equ    0x40        ; SDRAM Priority 4 offset
;SDRAM_SDPRY5            .equ    0x42        ; SDRAM Priority 5 offset
;SDRAM_SDPRY6            .equ    0x44        ; SDRAM Priority 6 offset
;SDRAM_SDPRY7            .equ    0x46        ; SDRAM Priority 7 offset
;SDRAM_SDPRY8            .equ    0x48        ; SDRAM Priority 8 offset
;SDRAM_SDPRY9            .equ    0x4A        ; SDRAM Priority 9 offset
;SDRAM_SDPRY10           .equ    0x4C        ; SDRAM Priority 10 offset
;SDMODE_VAL              .equ    0xB280      ; SDRAM config - DQM Control = force '1'
;REFCTL_VAL              .equ    0x0140      ; Refresh command sent after every 145*8 SDRAM clock cycles

;SDMODE_NOP              .equ    0x0000      ; SDRAM initialization - NOP 
;SDMODE_MSR              .equ    0x0001      ; SDRAM initialization - Mode Status Register Set 
;SDMODE_PREA             .equ    0x0002      ; SDRAM initialization - Precharge All 
;SDMODE_AUTOREF          .equ    0x0004      ; SDRAM initialization - AutoRefresh 
;SDMODE_AUTOPDN          .equ    0x0040      ; SDRAM initialization - Auto PowerDown 
;SDMODE_EMRS             .equ    0x0011      ; SDRAM initialization - Extended Mode Register Set 
;SDMODE_DSNORM           .equ    0x0011      ; SDRAM initialization - Drive Strength = Normal 
;SDMODE_DSHALF           .equ    0x0111      ; SDRAM initialization - Drive Strength = 1/2 
;SDMODE_DSQUART          .equ    0x0211      ; SDRAM initialization - Drive Strength = 1/4 
  
;SDMODE_VALUE32          .equ    0x0000      ; SDRAM initialization for MSR for 32 bit mode and CAS latency of 2 cycles
;SDMODE_VALUE16          .equ    0x2000      ; SDRAM initialization for MSR for 16 bit mode and CAS latency of 2 cycles
;SDMODE_DQM              .equ    0x0080      ; SDRAM config - DQM Control bit 

;SDPRY1_VALUE            .equ    0x0100      ; Set the CCD as highest priority
;SDPRY2_VALUE            .equ    0x0040      ; Set the priority of the preview engine
;SDPRY3_VALUE            .equ    0x0001      ; Set hardware engine to lowest priority
;SDPRY4_VALUE            .equ    0x0100      ; Set the priority of the OSD
;SDPRY5_VALUE            .equ    0x0002      ; Set the priority of the external host request
;SDPRY6_VALUE            .equ    0x0004      ; Set the priority of the ARM CPU request
;SDPRY7_VALUE            .equ    0x0010      ; Set the priority of the External Memory SDRAM DMA1
;SDPRY8_VALUE            .equ    0x0008      ; Set the priority of the External Memory SDRAM DMA2
;SDPRY9_VALUE            .equ    0x0020      ; Set the priority of the Image buffer DMA request
;SDPRY10_VALUE           .equ    0x0080      ; Set the priority of SDRAM refresh

;PRIORITY_ON             .equ    0x1         ; Turn priority on
 
; SDRAM End address configuration
 
;DM320_AHB_SDRAMEA       .equ    0x60F04  
;DM320_AHB_SDRAMEA_VALUE .equ    0x2900000   ; 32 MB SDRAM - 0x900000-0x2900000 


;***********************************
;*      MACROS                     *
;***********************************

    ; This macro is used to unnest interrupts.  It switches to the correct
    ; interrupt mode (FIQ/IRQ), removes the interrupt controller mask registers
    ; off the interrupt stack, restores the interrupt controller mask values,
    ; and returns back to the mode it was in before invoking the macro.
    
;UNNEST_INTERRUPT .macro INT_MODE
    
    ; Switch to correct mode

;    MRS     r0,CPSR                         ; Pickup current CPSR
;    ORR     r0,r0,#LOCKOUT                  ; Lock-out interrupts
;    BIC     r1,r0,#MODE_MASK                ; Clear the mode bits (preserve
                                            ; current mode in r0)
;    ORR     r1,r1,#INT_MODE                 ; Set the new mode bits
;    MSR     CPSR,r1                         ; Switch to correct mode

    ; ************ START BOARD SPECIFIC SECTION **************
    
    ; Get interrupt masks from stack

;    LDMIA   sp!,{r1-r2}                     ; Get Level 1\2 mask registers
                                            
    ; Update mask registers                 
                                            
;    LDR     r3,INT_BASE_ADDRESS1            ; Get base address of interrupt registers
;    STRH    r1,[r3,#INT_EINT0]              ; Store value of Level 0 mask register
;    MOV     r1,r1,LSR #16
;    STRH    r1,[r3,#INT_EINT1]              ; Store value of Level 1 mask register
;    STRH    r2,[r3,#INT_EINT2]              ; Store value of Level 2 mask register

    ; ************ END BOARD SPECIFIC SECTION **************

    ; Return back to correct original mode with interrupts locked-out

;    MSR     CPSR,r0

    ; UNNEST_INTERRUPT END

;    .endm    


    ; This macro is used to unnest minimal context save interrupts.
    ; It removes the interrupt controller mask registers from the stack frame,
    ; restores the interrupt mask register values, restores the minimally
    ; saved registers (saved in INT_IRQ or INT_FIQ) and adjusts the
    ; stack pointer to its pre-interrupt state.
    
;UNNEST_MIN_INTERRUPT .macro    

    ; ************ START BOARD SPECIFIC SECTION **************
    
    ; Get interrupt masks from stack

;    LDR     r0,[sp,#MASK1_STACK_OFFSET]
;    LDR     r1,[sp,#MASK2_STACK_OFFSET]

    ; Update mask registers

;    LDR     r3,INT_BASE_ADDRESS1            ; Get base address of interrupt registers
;    STRH    r0,[r3,#INT_EINT0]              ; Store value of Level 0 mask register
;    MOV     r0,r0,LSR #16
;    STRH    r0,[r3,#INT_EINT1]              ; Store value of Level 1 mask register
;    STRH    r1,[r3,#INT_EINT2]              ; Store value of Level 2 mask register


    ; ************ END BOARD SPECIFIC SECTION **************

    ; Restore registers r0-r5 from stack

;    LDMIA   sp!,{r0-r5}

    ; Adjust stack to remove space saved
    ; for mask registers

;    ADD     sp,sp, #MASK_REG_SPACE

    ; UNNEST_MIN_INTERRUPT END

;    .endm    

;********************************************
;*  TC_TCB and TC_HCB STRUCT OFFSET DEFINES *
;********************************************
; Task / HISR control block offsets

TC_CREATED              .equ     0x00       ; Node for linking to created task list
TC_ID                   .equ     0x0C       ; Internal TCB ID
TC_NAME                 .equ     0x10       ; Task name
TC_STATUS               .equ     0x18       ; Task status
TC_DELAYED_SUSPEND      .equ     0x19       ; Delayed task suspension
TC_PRIORITY             .equ     0x1A       ; Task priority
TC_PREEMPTION           .equ     0x1B       ; Task preemption enable
TC_SCHEDULED            .equ     0x1C       ; Task scheduled count
TC_CUR_TIME_SLICE       .equ     0x20       ; Current time slice
TC_STACK_START          .equ     0x24       ; Stack starting address
TC_STACK_END            .equ     0x28       ; Stack ending address
TC_STACK_POINTER        .equ     0x2C       ; Task stack pointer
TC_STACK_SIZE           .equ     0x30       ; Task stack's size
TC_STACK_MINIMUM        .equ     0x34       ; Minimum stack size
TC_CURRENT_PROTECT      .equ     0x38       ; Current protection
TC_SAVED_STACK_PTR      .equ     0x3C       ; Previous stack pointer
TC_ACTIVE_NEXT          .equ     0x3C       ; Next activated HISR
TC_TIME_SLICE           .equ     0x40       ; Task time slice value
TC_ACTIVATION_COUNT     .equ     0x40       ; Activation counter
TC_HISR_ENTRY           .equ     0x44       ; HISR entry function
TC_HISR_SU_MODE         .equ     0x58       ; Sup/User mode indicator for HISRs
TC_HISR_MODULE          .equ     0x5C       ; Module identifier for HISR's
TC_SU_MODE              .equ     0xA8       ; Sup/User mode indicator for Tasks
TC_MODULE               .equ     0xAC       ; Module identifier for Tasks

; Priority control block offset

TC_TCB_PTR              .equ     0x00       ; Owner of protection
TC_THREAD_WAIT          .equ     0x04       ; Waiting thread flag

; End of low-level initialization constants.

; ** END ASM_DEFS.INC **