📄 l1_defty.h
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API d_dai_onoff;
API d_auxdac;
#if (ANLG_FAM == 1)
API d_vbctrl;
#elif ((ANLG_FAM == 2) || (ANLG_FAM == 3))
API d_vbctrl1;
#endif
API d_bbctrl;
// Monitoring tasks control (MCU <- DSP)
// FB task
API d_fb_det; // FB detection result. (1 for FOUND).
API d_fb_mode; // Mode for FB detection algorithm.
API a_sync_demod[4]; // FB/SB demod. result, (D_TOA,D_PM,D_ANGLE,D_SNR).
// SB Task
API a_sch26[5]; // Header + SB information, array of 5 words.
API d_audio_gain_ul;
API d_audio_gain_dl;
// Controller of the melody E2 audio compressor
API d_audio_compressor_ctrl;
// AUDIO module
API d_audio_init;
API d_audio_status;
// Audio tasks
// TONES (MCU -> DSP)
API d_toneskb_init;
API d_toneskb_status;
API d_k_x1_t0;
API d_k_x1_t1;
API d_k_x1_t2;
API d_pe_rep;
API d_pe_off;
API d_se_off;
API d_bu_off;
API d_t0_on;
API d_t0_off;
API d_t1_on;
API d_t1_off;
API d_t2_on;
API d_t2_off;
API d_k_x1_kt0;
API d_k_x1_kt1;
API d_dur_kb;
API d_shiftdl;
API d_shiftul;
API d_aec_ctrl;
API d_es_level_api;
API d_mu_api;
// Melody Ringer module
API d_melo_osc_used;
API d_melo_osc_active;
API a_melo_note0[4];
API a_melo_note1[4];
API a_melo_note2[4];
API a_melo_note3[4];
API a_melo_note4[4];
API a_melo_note5[4];
API a_melo_note6[4];
API a_melo_note7[4];
// selection of the melody format
API d_melody_selection;
// Holes due to the format melody E1
API a_melo_holes[3];
// Speech Recognition module
API d_sr_status; // status of the DSP speech reco task
API d_sr_param; // paramters for the DSP speech reco task: OOV threshold.
API d_sr_bit_exact_test; // bit exact test
API d_sr_nb_words; // number of words used in the speech recognition task
API d_sr_db_level; // estimate voice level in dB
API d_sr_db_noise; // estimate noise in dB
API d_sr_mod_size; // size of the model
API a_n_best_words[4]; // array of the 4 best words
API a_n_best_score[8]; // array of the 4 best scores (each score is 32 bits length)
// Audio buffer
API a_dd_1[22]; // Header + DATA traffic downlink information, sub. chan. 1.
API a_du_1[22]; // Header + DATA traffic uplink information, sub. chan. 1.
// V42bis module
API d_v42b_nego0;
API d_v42b_nego1;
API d_v42b_control;
API d_v42b_ratio_ind;
API d_mcu_control;
API d_mcu_control_sema;
// Background tasks
API d_background_enable;
API d_background_abort;
API d_background_state;
API d_max_background;
API a_background_tasks[16];
API a_back_task_io[16];
// GEA module defined in l1p_deft.h (the following section is overlaid with GPRS NDB memory)
API d_gea_mode_ovly;
API a_gea_kc_ovly[4];
#if (ANLG_FAM == 3)
// SYREN specific registers
API d_vbpop;
API d_vau_delay_init;
API d_vaud_cfg;
API d_vauo_onoff;
API d_vaus_vol;
API d_vaud_pll;
API d_togbr2;
#elif ((ANLG_FAM == 1) || (ANLG_FAM == 2))
API d_hole3_ndb[7];
#endif
// word used for the init of USF threshold
API d_thr_usf_detect;
// Encryption module
API d_a5mode; // Encryption Mode.
API d_sched_mode_gprs_ovly;
// 7 words are reserved for any possible mapping modification
API d_hole4_ndb[5];
// Ramp definition for Omega device
API a_ramp[16];
// CCCH/SACCH downlink information...(!!)
API a_cd[15]; // Header + CCCH/SACCH downlink information.
// FACCH downlink information........(!!)
API a_fd[15]; // Header + FACCH downlink information.
// Traffic downlink data frames......(!!)
API a_dd_0[22]; // Header + DATA traffic downlink information, sub. chan. 0.
// CCCH/SACCH uplink information.....(!!)
API a_cu[15]; // Header + CCCH/SACCH uplink information.
// FACCH downlink information........(!!)
API a_fu[15]; // Header + FACCH uplink information
// Traffic downlink data frames......(!!)
API a_du_0[22]; // Header + DATA traffic uplink information, sub. chan. 0.
// Random access.....................(MCU -> DSP).
API d_rach; // RACH information.
//...................................(MCU -> DSP).
API a_kc[4]; // Encryption Key Code.
// Integrated Data Services module
API d_ra_conf;
API d_ra_act;
API d_ra_test;
API d_ra_statu;
API d_ra_statd;
API d_fax;
API a_data_buf_ul[21];
API a_data_buf_dl[37];
// GTT API mapping for DSP code 34 (for test only)
#if (L1_GTT == 1)
API d_tty_status;
API d_ctm_detect_shift;
API d_tty2x_baudot_mod_amplitude_scale;
API d_tty2x_samples_per_baudot_stop_bit;
API d_tty_reset_buffer_ul;
API d_tty_loop_ctrl;
API p_tty_loop_buffer;
API d_ctm_mod_norm;
API d_tty2x_offset_normalization;
API d_tty2x_threshold_startbit;
API d_tty2x_threshold_diff;
API d_tty2x_duration_startdetect;
API d_tty2x_startbit_thres;
#else
API a_tty_holes[13];
#endif
API a_sr_holes0[409];
#if (L1_NEW_AEC)
// new AEC
API d_cont_filter;
API d_granularity_att;
API d_coef_smooth;
API d_es_level_max;
API d_fact_vad;
API d_thrs_abs;
API d_fact_asd_fil;
API d_fact_asd_mut;
API d_far_end_pow_h;
API d_far_end_pow_l;
API d_far_end_noise_h;
API d_far_end_noise_l;
#else
API a_new_aec_holes[12];
#endif // L1_NEW_AEC
// Speech recognition model
API a_sr_holes1[145];
// Correction of PR G23M/L1_MCU-SPR-15494
#if ((CHIPSET == 12) || (CHIPSET == 4) || (CODE_VERSION == SIMULATION))
API d_cport_init;
API d_cport_ctrl;
API a_cport_cfr[2];
API d_cport_tcl_tadt;
API d_cport_tdat;
API d_cport_tvs;
API d_cport_status;
API d_cport_reg_value;
API a_cport_holes[1011];
#else // CHIPSET != 12
API a_cport_holes[1020];
#endif // CHIPSET == 12
API a_model[1041];
// EOTD buffer
#if (L1_EOTD==1)
API d_eotd_first;
API d_eotd_max;
API d_eotd_nrj_high;
API d_eotd_nrj_low;
API a_eotd_crosscor[18];
#else
API a_eotd_holes[22];
#endif
// AMR ver 1.0 buffers
API a_amr_config[4];
API a_ratscch_ul[6];
API a_ratscch_dl[6];
API d_amr_snr_est; // estimation of the SNR of the AMR speech block
#if (L1_VOICE_MEMO_AMR)
API d_amms_ul_voc;
#else
API a_voice_memo_amr_holes[1];
#endif
API d_thr_onset_afs; // thresh detection ONSET AFS
API d_thr_sid_first_afs; // thresh detection SID_FIRST AFS
API d_thr_ratscch_afs; // thresh detection RATSCCH AFS
API d_thr_update_afs; // thresh detection SID_UPDATE AFS
API d_thr_onset_ahs; // thresh detection ONSET AHS
API d_thr_sid_ahs; // thresh detection SID frames AHS
API d_thr_ratscch_marker; // thresh detection RATSCCH MARKER
API d_thr_sp_dgr; // thresh detection SPEECH DEGRADED/NO_DATA
API d_thr_soft_bits;
#if ((CODE_VERSION == SIMULATION) || (DSP != 37))
#if (MELODY_E2)
API d_melody_e2_osc_stop;
API d_melody_e2_osc_active;
API d_melody_e2_semaphore;
API a_melody_e2_osc[16][3];
API d_melody_e2_globaltimefactor;
API a_melody_e2_instrument_ptr[8];
API d_melody_e2_deltatime;
#else
API d_melody_e2_holes[61];
#endif
#else // (DSP == 37)
API a_amrschd_debug[30]; // 0x1500
#if (W_A_AMR_THRESHOLDS)
API a_d_macc_thr_afs[8]; // 0x151E
API a_d_macc_thr_ahs[6]; // 0x1526
#else
API a_d_macc_thr_holes[14]; // 0x151E
#endif
API d_melody_e2_holes[17]; //0x152C - This is not a melody E2 hole; But named like that;
#endif
#if ((CHIPSET == 12) || (CHIPSET == 4) || ((CHIPSET == 10) && (OP_WCP == 1)) || (CODE_VERSION == SIMULATION)) // Calypso+ or Perseus2 or Samson
API d_vol_ul_level;
API d_vol_dl_level;
API d_vol_speed;
API d_sidetone_level;
// Audio control area
API d_es_ctrl;
API d_anr_ul_ctrl;
#if ((DSP == 36) || (DSP == 37))
API d_aqi_ctrl_hole1_1[3];
#if (L1_SAIC != 0)
API d_swh_flag_ndb;
API d_swh_Clipping_Threshold_ndb;
#else
API d_swh_hole[2];
#endif
API d_aqi_ctrl_hole1_2[1];
#else
API d_aqi_ctrl_hole1[6]; // Reserved for future UL modules
#endif
API d_iir_dl_ctrl;
API d_lim_dl_ctrl;
API d_aqi_ctrl_hole2[4]; // Reserved for future DL modules
API d_aqi_status;
#if (L1_IIR == 1)
API d_iir_input_scaling;
API d_iir_fir_scaling;
API d_iir_input_gain_scaling;
API d_iir_output_gain_scaling;
API d_iir_output_gain;
API d_iir_feedback;
API d_iir_nb_iir_blocks;
API d_iir_nb_fir_coefs;
API a_iir_iir_coefs[80];
API a_iir_fir_coefs[32];
#else
API d_iir_hole[120];
#endif
#if (L1_ANR == 1)
API d_anr_min_gain;
API d_anr_vad_thr;
API d_anr_gamma_slow;
API d_anr_gamma_fast;
API d_anr_gamma_gain_slow;
API d_anr_gamma_gain_fast;
API d_anr_thr2;
API d_anr_thr4;
API d_anr_thr5;
API d_anr_mean_ratio_thr1;
API d_anr_mean_ratio_thr2;
API d_anr_mean_ratio_thr3;
API d_anr_mean_ratio_thr4;
API d_anr_div_factor_shift;
API d_anr_ns_level;
#else
API d_anr_hole[15];
#endif
#if (L1_LIMITER == 1)
API a_lim_mul_low[2];
API a_lim_mul_high[2];
API d_lim_gain_fall_q15;
API d_lim_gain_rise_q15;
API d_lim_block_size;
API d_lim_nb_fir_coefs;
API d_lim_slope_update_period;
API a_lim_filter_coefs[16];
#else
API d_lim_hole[25];
#endif
#if (L1_ES == 1)
API d_es_mode;
API d_es_gain_dl;
API d_es_gain_ul_1;
API d_es_gain_ul_2;
API d_es_tcl_fe_ls_thr;
API d_es_tcl_dt_ls_thr;
API d_es_tcl_fe_ns_thr;
API d_es_tcl_dt_ns_thr;
API d_es_tcl_ne_thr;
API d_es_ref_ls_pwr;
API d_es_switching_time;
API d_es_switching_time_dt;
API d_es_hang_time;
API a_es_gain_lin_dl_vect[4];
API a_es_gain_lin_ul_vect[4];
#else
API d_es_hole[21];
#endif
#else // CALYPSO+ or PERSEUS2
API a_calplus_holes[200];
#endif
#if (W_A_AMR_THRESHOLDS)
API d_holes[492];
#if (CODE_VERSION == SIMULATION) || (DSP != 37)
API a_d_macc_thr_afs[8]; // In ROM37 this is moved from 0x17F1 to 0x151E
API a_d_macc_thr_ahs[6];
#else
API d_holes_rom37[14]; // In ROM37 this is moved from 0x17F1 to 0x151E
#endif
API d_one_hole[1];
#else
API d_holes[507];
#endif
#if (MELODY_E2)
API a_dsp_trace[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_DSP_TRACE];
API a_melody_e2_instrument_wave[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_INSTRUMENT];
#endif
}
T_NDB_MCU_DSP;
#elif (DSP == 33) // NDB GSM
typedef struct
{
// MISC Tasks
API d_dsp_page;
// DSP status returned (DSP --> MCU).
API d_error_status;
// RIF control (MCU -> DSP).
API d_spcx_rif;
API d_tch_mode; // TCH mode register.
// bit [0..1] -> b_dai_mode.
// bit [2] -> b_dtx.
API d_debug1; // bit 0 at 1 enable dsp f_tx delay for Omega
API d_dsp_test;
// Words dedicated to Software version (DSP code + Patch)
API d_version_number1;
API d_version_number2;
API d_debug_ptr;
API d_debug_bk;
API d_pll_config;
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